• Journal of information and communication convergence engineering
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• v.18 no.2
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• pp.115-122
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• 2020

Audiovisual (AV) facilities such as TVs and signage are installed in various public places. However, audio cannot be used to prevent noise and interference from individuals, which results in a loss of concentration and understanding of AV content. To address this problem, a total technique for remotely listening to audio from audiovisual facilities with clean sound quality while maintaining video and lip-syncing through personal smart mobile devices is proposed in this paper. Through the experimental results, the proposed scheme has been verified to reduce system power consumption by 8% to 16% and provide real-time processing with a low latency of 120 ms. The system described in this paper will contribute to the activation of audio telehearing services as it is possible to provide audio remote services in various places, such as express buses, trains, wide-area and intercity buses, public waiting rooms, and various application services.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.10 no.8
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• pp.3551-3567
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• 2016

The Low Earth Orbit satellite network has the unique characteristics of the non-uniform and time-variant traffic load distribution, which often causes severe link congestion and thus results in poor performance for delay-sensitive flows, especially when the network is heavily loaded. To solve this problem, a novel adaptive routing algorithm, referred to as the delay-oriented adaptive routing algorithm (DOAR), is proposed. Different from current reactive schemes, DOAR employs Destination-Sequenced Distance-Vector (DSDV) routing algorithm, which is a proactive scheme. DSDV is extended to a multipath QoS version to generate alternative routes in active with real-time delay metric, which leads to two significant advantages. First, the flows can be timely and accurately detected for route adjustment. Second, it enables fast, flexible, and optimized QoS matching between the alternative routes and adjustment requiring flows and meanwhile avoids delay growth caused by increased hop number and diffused congestion range. In addition, a retrospective route adjustment requesting scheme is designed in DOAR to enlarge the alternative routes set in the severe congestion state in a large area. Simulation result suggests that DOAR performs better than typical adaptive routing algorithms in terms of the throughput and the delay in a variety of traffic intensity.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.39C no.5
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• pp.435-446
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• 2014

Even if it is important to transmit high rate multimedia information without any transmission errors for surveillance systems, it is difficult to achieve error-free transmission due to infra-less adhoc networks. In order to reduce the transmission errors furthermore, additional signal overheads or retransmission of signals should be required, but they may lead to transmission delay. This paper represents a study on low delay and adaptive video transmission for the unmanned surveillance systems by developing system protocols. In addition, we introduce an efficient and adaptive control algorithm using system parameters for exploiting unmanned surveillance system properly over multi-channels.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.4
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• pp.72-78
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• 2009

This paper proposes a low phase noise ring voltage controlled oscillator(VCO) with a standard $0.13{\mu}m$ CMOS process for PLL circuit using the VCO-gain-controlled Delay cell. The proposed Delay cell architecture with a active resistor using a MOS transistor. This method can reduced a VCO gain so that improve phase noise. And, Delay cell consist of Wide-Swing Cascode current mirror, Positive Latch and Symmetric load for low phase noise. The measurement results demonstrate that the phase noise is -119dBc/Hz at 1MHz offset from 1.9GHz. The VCO gain and power dissipation are 440MHz/V and 9mW, respectively.

• The Journal of the Korea institute of electronic communication sciences
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• v.9 no.9
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• pp.971-976
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• 2014

In this paper, we proposed a low power algorithm using state transition ready method. The proposed algorithm defined a sleep state, a idle state and a run state for the task. A state transition occurring at the time due to the delay time created in order to reduce the power consumption state in the middle of each inserted into the ready state. The ready state considering a power consumption and a delay time in state transition. A scheduling step of performing the steps in excess of the increasing problems have the delay time is long. The power consumption increased for the operation step increase. A state transition from a sleep state with the longest delay time in operating state occurs when the state is switched by the time delay caused by the increase in operating time reduces the overall power consumption reduced. Experiments [6] were compared with the results of the power consumption. The experimental results [6] is reduced power consumption than the efficiency of the algorithm has been demonstrated.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.49 no.4
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• pp.82-88
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• 2012

A VANET (Vehicular Ad Hoc Network), a subclass of MANET (Mobile Ad Hoc Network), is an ad hoc network using wireless communication between vehicles without fixed infrastructure such as base station. VANET suffers a frequent link breakage and network topology change because of the rapid movement of vehicles and the density change of vehicles. From these characteristics of VANET, geographical routing protocols such as GPSR (Greedy Perimeter Stateless Routing) using only the information of neighbor nodes are more suitable rather than AODV and DSR that are used in existing MANETs. However, GPSR may have a transmission delay and packet loss by frequent link disconnection and continual local maxima under the low vehicle density conditions. Therefore, in this paper, we propose a DTVR (Delay Tolerant Vehicular Routing) algorithm that perform a DTN-based routing scheme if there is no 2-hop neighbor nodes for efficient routing under the low vehicle densities in VANETs. Simulation results using ns-2 reveal that the proposed DTVR protocol performs much better performance than the existing routing protocols.

• The Journal of the Korea institute of electronic communication sciences
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• v.18 no.2
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• pp.291-298
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• 2023

SRAM-based in-memory computing is one of the technologies to solve the bottleneck of von Neumann architecture. In order to achieve SRAM-based in-memory computing, it is essential to design efficient SRAM bit-cell. In this paper, we propose a low-power differential sensing 8+T SRAM bit-cell which reduces power consumption and improves circuit performance. The proposed 8+T SRAM bit-cell is applied to ripple carry adder which performs SRAM read and bitwise operations simultaneously and executes each logic operation in parallel. Compared to the previous work, the designed 8+T SRAM-based ripple carry adder is reduced power consumption by 11.53%, but increased propagation delay time by 6.36%. Also, this adder is reduced power-delay-product (PDP) by 5.90% and increased energy-delay- product (EDP) by 0.08%. The proposed circuit was designed using TSMC 65nm CMOS process, and its feasibility was verified through SPECTRE simulation.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.2 s.332
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• pp.41-48
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• 2005

In this paper, we propose a new Low-Swing CVSL full adder for low power consumption. An $8\times8$ parallel multiplier is used for the comparison between the proposed Low-Swing CVSL full adder with conventional CVSL full adder. Comparing the previous works, this circuit is reduced the power consumption rate of $13.1\%$ and the power-delay-product of $14.3\%$. The validity and effectiveness of the proposes circuits are verified through the HSPICE under Hynix $0.35{\mu}m$ standard CMOS process.

• 제어로봇시스템학회:학술대회논문집
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• 2005.06a
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• pp.1571-1576
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• 2005

DCS has many processing components and various communication elements. And its communication delay characteristic is affected diverse operating situation and context. Especially, binding signal which traversed from one control-node to another control-node undergo all sort of delay conditions. So its delay value has large deviation with the lapse of time, and the measurement of delay statistics during long time is very difficult by using general oscilloscope or other normal instruments. This thesis introduces the design and implementation of PC-based BDAS(Binding Delay Analysis System) System developed to overcomes these hardships. The system has signal-generator, IO-card, data-acquisition module, delay-calculation and analyzer module, those are implemented on industrial standard PC/Ethernet hardware and Windows/Linux platforms. This system can detect accurate whole-system-wide delay time including io, control processing and network delay, in the resolution of msec unit, and can analyze each channel's delay-historic data which is maintained by realtime database. So, this system has strong points of open system architecture, for example, user-friendly environment, low cost, high compatibility, simplicity of maintenance and high extension ability. Of all things, the measuring capability of long-time delay-statistics obtained through historic-DB make the system more valuable and useful, which function is essential to analyze accurate delay performance of DCS system. Using this system, the verification of delay performance of DCS for nuclear power plants is succeeded in KNICS(Korea Nuclear Instrumentation & Control System) projects

• Journal of the Korea Institute of Military Science and Technology
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• v.14 no.5
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• pp.842-849
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• 2011

The transponder simulator designed to simulate the transponder of military satellite communication systems in the geostationary orbit is required to have time delay function, because of 250 ms delay time, when a radio wave transmits the distance of 36,000 km in free space. But, it is very difficult to develop 250 ms time delay device in the transponder simulator of 100 MHz bandwidth, due to unstable operation of FPGA, loss of memory data for the high speed rate signal processing. Up to date, bandwidth of the time delay device is limited to 45 MHz bandwidth. To solve this problem, we propose the new time delay techniques up to 100 MHz bandwidth without data loss. Proposed techniques are the low speed down scaling and high speed up scaling methods to read and write the external memory, and the matrix structure design of FPGA memory to treat data as high speed rate. We developed the satellite link simulator in 100 MHz bandwidth using the proposed new time delay techniques, implemented to the transponder simulator and verified the function of 265 ms time delay device in 100 MHz bandwidth.