• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2001년도 하계종합학술대회 논문집(2)
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• pp.281-284
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• 2001

This paper describes an analog multi-phase delay-locked loop (DLL) to solve the harmonic lock problem using current-starved inverter and shunt-capacitor delay cell. The DLL can be used not only as an internal clock buffer of microprocessors and memory It's but also as a multi-phase clock generator for gigabit serial interfaces. The proposed circuit was simulated in a 0.25${\mu}{\textrm}{m}$ CMOS technology to solve harmonic lock problem and to realize fast lock-on time and low-jitter we verified time interval less than 40 ps as the simulation results.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1999년도 추계종합학술대회 논문집
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• pp.392-395
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• 1999

The state assignment for a finite state machine greatly affects the delay, area, and testabilities of the sequential circuits. In order to minimize the dependencies among state variables, therefore possibly to reduce the length and number of feedback cycles, a new state assignment technique based on m-block partition is introduced in this paper. After the completion of state assignment and logic synthesis, partial scan design is performed to choose minimal number of scan flip-flops. Experiment shows drastic improvement in testabilities while preserving low area and delay overhead.

• 전자공학회논문지B
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• 제32B권11호
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• pp.1481-1488
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• 1995

Due to the low loss, broadband and accurate short time delay properties of optical fiber, it has attracted as a delay medium for high speed and broad-band signal processing. In this paper, we consider the coherent optical fiber filter of IIR lattice structure, which uses coherent light sources and consists of directional couplers whose coupling coefficients are restricted between 0 and 1. Considering restrictions of directional coupler, the design formulae and condition for realibility of optical fiber filter of IIR lattice structure which makes the optimal use of optical signal energy are derived.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 추계종합학술대회 논문집(2)
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• pp.83-86
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• 2000

This paper describes a delay-locked loop(DLL_) with low-jitter using Vernier Method. This DLL can be used to synchronize the internal clock to the external clock with very short time interval and fast lock-on. The proposed circuit was simulated in a 0.25 $\mu\textrm{m}$ CMOS technology to realize low-jitter. We verified 50-ps of time interval within 5 clock cycles of the clock as the simulation results.

• 정보처리학회논문지A
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• 제15A권5호
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• pp.243-248
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• 2008

본 논문은 다중 문턱전압 CMOS를 이용하여 저 전력 특성을 갖는 캐리 예측 가산기 (carry look-ahead adder)를 설계하였으며, 이를 일반적인 CMOS 가산기와 특성을 비교하였다. 전파 지연시간이 긴 임계경로에 낮은 문턱전압 트랜지스터를 사용하여 전파 지연시간을 감소시켰다. 전파 지연시간이 짧은 최단경로에는 높은 문턱전압 트랜지스터를 사용하여 회로전체의 소비전력을 감소시켰으며, 그 외의 논리블럭들은 정상 문턱전압의 트랜지스터를 사용하였다. 설계한 가산기는 일반적인 CMOS 회로와 비교하여 소비전력에서 14.71% 감소하였으며, 소비전력과 지연 시간의 곱에서 16.11%의 성능향상이 있었다. 이 회로는 삼성 $0.35{\mu}m$ CMOS 공정을 이용하여 설계하였으며, HSPICE를 통하여 검증하였다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2003년도 하계종합학술대회 논문집 II
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• pp.1169-1172
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• 2003

In this paper, a CLB-based CPLD low-power technology mapping algorithm consider area and delay time is proposed. To perform low power technology mapping for CPLD, a given Boolean network have to be represented to DAG. The proposed algorithm are consist of three step. In the first step, TD(Transition Density) calculation have to be performed. In the second step, the feasible clusters are generated by considering the following conditions: the number of output, the number of input and the number of OR-terms for CLB(Common Logic Block) within a CPLD. The common node cluster merging method, the node separation method, and the node duplication method are used to produce the feasible clusters. In the final step, low power technology mapping based on the CLBs is packing the feasible clusters into the several proper CLBs. The proposed algorithm is examined by using benchmarks in SIS. In the case of that the number of OR-terms is 5, the experiments results show that reduce the power consumption by 30.73% comparing with that of TEMPLA, and 17.11% comparing with that of PLAmap respectively.

• Journal of Electrical Engineering and Technology
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• 제9권1호
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• pp.27-36
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• 2014

This paper presents an adaptive wide-area damping controller (WADC) based on generalized predictive control (GPC) and model identification for damping the inter-area low frequency oscillations in large-scale inter-connected power system. A recursive least-squares algorithm (RLSA) with a varying forgetting factor is applied to identify online the reduced-order linearlized model which contains dominant inter-area low frequency oscillations. Based on this linearlized model, the generalized predictive control scheme considering control output constraints is employed to obtain the optimal control signal in each sampling interval. Case studies are undertaken on a two-area four-machine power system and the New England 10-machine 39-bus power system, respectively. Simulation results show that the proposed adaptive WADC not only can damp the inter-area oscillations effectively under a wide range of operation conditions and different disturbances, but also has better robustness against to the time delay existing in the remote signals. The comparison studies with the conventional lead-lag WADC are also provided.

• 대한전기학회논문지:전기물성ㆍ응용부문C
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• 제55권12호
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• pp.601-605
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• 2006

The resistance-capacitance (RC) delay of signals through interconnection materials becomes a big hurdle for high speed operation of semiconductors which contain multi-layer interconnections in smaller scales with higher integration density. Low-k materials are applied to the inter-metal dielectric (IMD) materials in order to overcome the RC delay. Relaxation continuum (RCT) model that includes neutral-species transport model have developed to model the etching process in a capacitively coupled plasma (CCP) device. We present the parametric study of the modeling results of a two-frequency capacitively coupled plasma (2f-CCP) with $N_2/H_2$ gas mixture that is known as promising one for organic low-k materials etching. For the etching of low-k materials by $N_2/H_2$ plasma, N and H atoms have a big influence on the materials. Moreover the distributions of excited neutral species influence the plasma density and profile. We include the neutral transport model as well as plasma one in the calculation. The plasma and neutrals are calculated self-consistently by iterating the simulation of both species till a spatio-temporal steady state profile could be obtained.

• Journal of Electrical Engineering and Technology
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• 제9권3호
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• pp.1080-1088
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• 2014

By combining a wind turbine with an energy storage system (ESS), we are able to attenuate the intermittent wind power characteristic making the power derived from a wind farm dispatchable. This paper evaluates the influence of the phase delay of the low-pass filter in the conventional smoothing power control on the ESS capacity; longer phase delays require a larger ESS capacity. In order to eliminate the effect of the phase delay, we optimize the power dispatch using a zero-phase low-pass filter that results in a non-delayed response in the power dispatch. The proposed power dispatching method significantly minimizes the ESS capacity. In addition, the zero-phase low-pass filter, which is a symmetrical forward-reverse finite impulse response type, is designed simply with a small number of coefficients. Therefore, the proposed dispatching method is not only optimal, but can also be feasibly applied to real wind farms. The efficacy of the proposed dispatching method is verified by integrating a 3 MW wind turbine into the grid using wind data measured on Jeju Island.

• 정보처리학회논문지:컴퓨터 및 통신 시스템
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• 제2권6호
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• pp.265-278
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• 2013

최근 다양한 무선 통신기술이 발전됨에 따라 네트워크 자원을 효율적으로 사용하기 위하여 모바일 멀티캐스트 기법의 중요성이 부각되고 있다. 기존에는 멀티캐스트 서비스를 위한 네트워크 전달 비용적 측면과 멀티캐스트 핸드오버 지연 최소화에 중점을 두고 모바일 IP기반의 다양한 멀티캐스팅 기법들이 제안되었다. 그러나 호스트 기반의 이동성 관리 기술인 MIPv6(Mobile IPv6)를 이용한 기법들은 근본적으로 핸드오버의 지연과 터널 컨버전스 문제를 해결하기 어렵다. 이러한 문제점을 해결하기 위해서 네트워크 기반의 이동성 관리 기술인 PMIPv6(Proxy Mobile IPv6)를 표준화하였다. PMIPv6는 MIPv6에 비해서 성능이 향상되었지만 여전히 핸드오버 지연과 터널 컨버전스 등의 문제를 가지고 있다. 본 논문에서는 이러한 한계를 해결하기 위하여 PMIPv6 네트워크에서 멀티캐스팅을 지원하는 저비용의 빠른 이동성관리를 위한 LFH(Low-Cost and Fast Handoff) 기법을 제안한다. 복잡한 멀티캐스트 라우팅 프로토콜과 멀티캐스트 구성원 메시지의 상호작용을 줄이기 위해 간소화된 MLD(Multicast Listener Discovery) 프록시 기능을 구현하고 MLD 기능을 수정한다. 그리고 LMA(Local Mobility Anchor) 도메인 내에서의 멀티캐스트 핸드오버 절차와 도메인 간에서의 멀티캐스트 핸드오버 절차에 TCR(Tunnel Combination and Reconstruction) 알고리즘을 사용하여 터널 컨버전스 문제를 해결한다. 그 결과 LFH 기법의 성능이 다른 멀티캐스트 방식과 비교하여 멀티캐스트 중단시간을 줄여주어 더 적은 비용이 든다는 것을 보여준다.