• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
• /
• v.29 no.3
• /
• pp.61-68
• /
• 2015

When medium and large induction motors are driven by 2-level inverters with low switching frequency, induction motors provoke deteriorated performances resulted from large torque ripples, flux ripples, and large current distortion. Model predictive torque control(MPTC) for a fast torque control of induction motors is also suffered from large torque ripples when the induction motors are fed by 2-level inverters that are based on 6 active voltage vectors with low switching frequency restricted. To solve this problem, this paper proposes a new MPTC method based on both a 12 active voltage vector and an optimized duty ratio calculation. The proposed control strategy illustrates its effectiveness under the various operating conditions through simulation works.

• Journal of Power Electronics
• /
• v.17 no.3
• /
• pp.601-609
• /
• 2017

Gallium nitride (GaN) power switching devices are promising candidates for high switching frequency and high efficiency power conversion due to their fast switching, low on-state resistance, and high-temperature operation capability. In order to facilitate the use of these new devices better, it is required to investigate the device characteristics and performance in detail preferably by comparing with various conventional silicon (Si) devices. This paper presents a comprehensive study of GaN high electron mobility transistor (HEMT) based non-isolated point-of-load (POL) synchronous buck converter operating at 2.7 MHz with a high step-down ratio (24 V to 3.3 V). The characteristics and performance of GaN HEMT and three different Si devices are analytically investigated and the optimal operating point for GaN HEMT is discussed. Zero-voltage switching (ZVS) is implemented to minimize switching loss in high switching frequency operation. The prototype circuit and experimental data support the validity of analytical and simulation results.

• KIEE International Transaction on Electrical Machinery and Energy Conversion Systems
• /
• v.5B no.4
• /
• pp.366-373
• /
• 2005

This paper presents two new circuit topologies of the dc busline side active resonant snubber assisted voltage source high frequency link soft switching PWM full-bridge dc-dc power converters acceptable for either utility ac 200V-rms or ac 400V-rms input grid. These high frequency switching dc-dc converters proposed in this paper are composed of a typical voltage source-fed full-bridge PWM inverter, high frequency transformer with center tap, high frequency diode rectifier with inductor input filter and dc busline side series switches with the aid of a dc busline parallel capacitive lossless snubber. All the active switches in the full-bridge arms as well as dc busline snubber can achieve ZCS turn-on and ZVS turn-off transition commutation with the aid of a transformer leakage inductive component and consequently the total switching power losses can be effectively reduced. So that, a high switching frequency operation of IGBTs in the voltage source full bridge inverter can be actually designed more than about 20 kHz. It is confirmed that the more the switching frequency of full-bridge soft switching inverter increases, the more soft switching PWM dc-dc converter with a high frequency transformer link has remarkable advantages for its power conversion efficiency and power density implementations as compared with the conventional hard switching PWM inverter type dc-dc power converter. The effectiveness of these new dc-dc power converter topologies can be proved to be more suitable for low voltage and large current dc-dc power supply as arc welding equipment from a practical point of view.

• Proceedings of the KIPE Conference
• /
• 2015.11a
• /
• pp.149-150
• /
• 2015

This paper presents narrowband voltage controller for large capacity UPS system with low switching frequency. The proposed controller is repetitive controller applicable to low sampling. The controller reduces the control error for nonlinear load and improve efficiency. The proposed controller is verified through the experiment using 40kW UPS inverter.

• Journal of Power Electronics
• /
• v.9 no.3
• /
• pp.396-402
• /
• 2009

A DC/DC converter generally needs to work under high switching frequency when used as an adjustable power supply to reduce the size of magnetic elements such as inductors, transformers and capacitors, but with the rising of the switch frequency, the switch losses will increase and the efficiency will reduce. Recently, to solve these problems, research is actively being done on a soft switching method that can be applied under high frequency and on a PWM converter that can be applied under low frequency such as a multi-level topology. In this paper a novel DC-DC conversion method for reducing the ripple of output voltage is proposed. In the proposed converter, buck converters are connected in series to generate the output voltage. By using this method, the ripple of output voltage can be reduced compared to a conventional buck converter. Particularly when output voltage is low, the number of acting switching elements is less and the result of ripple reduction is more obvious. It is expected that the converter proposed in this paper could be very useful in the case of wide-range output voltage.

• Journal of Power Electronics
• /
• v.16 no.2
• /
• pp.498-511
• /
• 2016

This paper presents a single-phase five-level inverter controlled by two novel pulse width modulation (PWM) switching techniques. The proposed PWM techniques are designed based on minimum switching power loss and minimum total harmonic distortion (THD). In a single-phase five-level inverter employing six switches, the first proposed PWM technique requires four switches to operate at switching frequency and two other switches to operate at line frequency. The second proposed PWM technique requires only two switches to operate at switching frequency and the rest of the switches to operate at line frequency. Compared with conventional PWM techniques for single-phase five-level inverters, the proposed PWM techniques offer high efficiency and low harmonic components in the output voltage. The validity of the proposed PWM switching techniques in controlling single-phase five-level inverters to regulate load voltage is verified experimentally using a 100 V, 500 W laboratory prototype controlled by dspace 1103.

• The Transactions of the Korean Institute of Power Electronics
• /
• v.22 no.2
• /
• pp.181-184
• /
• 2017

This study analyzes the turn-on and turn-off transients of a metal-oxide-semiconductor field-effect transistor (MOSFET) with high-switching frequency systems. In these systems, the voltage distortion becomes serious at the output terminal of a Vienna rectifier by the turn-off delay of the MOSFET. The current has low-order harmonics through this voltage distortion. This paper describes the transient of the turn-off that causes the voltage distortion. The algorithm for reducing the sixth harmonic using a proportional-resonance controller is proposed to improve the current distortion without complex calculation for compensation. The reduction of the current distortion by high-switching frequency is verified by experiment with the 2.5-kW prototype Vienna rectifier.

• Journal of Power Electronics
• /
• v.14 no.3
• /
• pp.531-540
• /
• 2014

A novel carrier-based PWM (CBPWM) strategy of a three-level NPC converter is proposed in this paper. The novel strategy can eliminate the low-frequency neutral point (NP) voltage oscillation under the entire modulation index and full power factor. The basic principle of the novel strategy is introduced. The internal modulation wave relationship between the novel CBPWM strategy and traditional SPWM strategy is also studied. All 64 modulation wave solutions of the CBPWM strategy are derived. Furthermore, the proposed CBPWM strategy is compared with traditional SPWM strategy regarding the output phase voltage THD characteristics, DC voltage utilization ratio, and device switching losses. Comparison results show that the proposed strategy does not cause NP voltage oscillation. As a result, no low-frequency harmonics occur on output line-to-line voltage and phase current. The novel strategy also has higher DC voltage utilization ratio (15.47% higher than that of SPWM strategy), whereas it causes larger device switching losses (4/3 times of SPWM strategy). The effectiveness of the proposed modulation strategy is verified by simulation and experiment results.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.14 no.8
• /
• pp.809-815
• /
• 2003

It is very important to get very high switching speed as well as low phase noise of frequency synthesizer in the OFDM/FH communication system. In this paper we compare the phase noises and switching speeds of the conventional PLL and digital hybrid PLL(DH-PLL) frequency synthesizer, also, we investigate the effect of phase noise on the performance of OFDM/FH communication system. DH-PLL has high switching speed property at the cost of circuit complexity and more power consumption. Unlike the conventional PLL in which the phase noise and switching speed have the trade off relationship in respect of loop filter bandwidth, DH-PLL frequency synthesizer can perform fast switching speed and low phase noise simultaneously. Under the condition of same hopping speed requirement, DH-PLL can achieve faster switching speed and lower SNR penalty compared with conventional PLL in the OFDM/FH communication system.

• Journal of Electrical Engineering and Technology
• /
• v.11 no.6
• /
• pp.1656-1663
• /
• 2016

A capacitive wireless power transfer (C-WPT) system uses an electric field to transmit power through a physical isolation barrier which forms a pair of ac link capacitors between the metal plates. However, the physical dimension and low dielectric constant of the interface medium severely limit the effective link capacitance to a level comparable to the main switch output capacitance of the transmitting circuit, which thus narrows the soft-switching range in the light load condition. Moreover, by fundamental limit analysis, it can be proved that such a low link capacitance increases operating frequency and capacitor voltage stress in the full load condition. In order to handle these problems, this paper investigates optimal design of double matching transformer networks for C-WPT. Using mathematical analysis with fundamental harmonic approximation, a design guideline is presented to avoid unnecessarily high frequency operation, to suppress the voltage stress on the link capacitors, and to achieve wide ZVS range even with low link capacitance. Simulation and hardware implementation are performed on a 5-W prototype system equipped with a 256-pF link capacitance and a 200-pF switch output capacitance. Results show that the proposed scheme ensures zero-voltage-switching from full load to 10% load, and the switching frequency and the link capacitor voltage stress are kept below 250 kHz and 452 V, respectively, in the full load condition.