• 제목/요약/키워드: Low Resistance Switch

검색결과 50건 처리시간 0.021초

초저저항 MOS 스위치의 최적 배치설계 (Optimal Layout Methods for MOSFETs of Ultra Low Resistance)

  • 김준엽
    • 대한전기학회논문지:시스템및제어부문D
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    • 제51권12호
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    • pp.596-603
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    • 2002
  • New layout methods for implementing MOS switches of ultra low channel resistance are presented. These area-effective layout methods include the waffle structure, zipper structure, star zag structure and fingered waffle structure. The design equations for these new layout structures are analyzed. The area-effectiveness of these structures is compared with that of the conventional alternating bar structure. MOS switches of the waffle structure were fabricated using a standard 0.25um CMOS process. The experimental characterization results of the fabricated MOS switches are presented. The analytical comparison and experimental results show that area reductions over 40% are achievable with the new structures.

Pull-in과 release 전압차 감소용 돌기구조를 갖는 비틀림형 초소형 기계적 스위칭 소자 (Torsional Micromechanical Switching Element Including Bumps for Reducing the Voltage Difference Between Pull-in and Release)

  • 하종민;한승오;박정호
    • 대한전기학회논문지:전기물성ㆍ응용부문C
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    • 제50권9호
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    • pp.471-475
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    • 2001
  • ln this paper, a micromachined micromechanical switch is presented. The presented switch is operated in the vertical direction to the substrate by an electrostatic force between two parallel plates. The moving plate is pulled down to connect the bumps of the bias node$(V_{DD}/ or GND)$ to the bumps of the output node when a oltage difference exists between the moving plate and the input plate. The switch was designed to operate at a low switching voltage$(\risingdotseq5V)$ by including a large-area, narrow-gap, parallel plate capacitor A theoretical analysis of the designed switch was performed in order to determine its geometry fitting the desired pull-in voltage and release voltage. The designed switch was fabricated by surface micromachining combined with Ni electroplating. From the experimental results of the fabricated switch, its pull-in voltage came Out to be less than 5V and the measured maximum allowable current was 150mA. The measured average ON-state resistance was about 8$\Omega$, and the OFF-state resistance was too high to be measured with digital multimeter.

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구형파 구동 BLDCM의 동기정류를 사용한 인버터 손실 저감 (Inverter Losses Reduction for Rectangular Drive BLDCM using Synchronous Rectification)

  • 남명준;김학원;조관열
    • 전력전자학회논문지
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    • 제21권2호
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    • pp.117-125
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    • 2016
  • In this paper, the inverter switch losses of BLDC motor for three types of PWM methods and power devices were analyzed. When the BLDC motor is driven at low currents, the inverter switch losses for MOSFET are low because MOSFET operates like resistance. However, the inverter switch losses for IGBT are higher than MOSFET due to its large turn-off losses. Moreover, synchronous rectification switching method is adaptable because MOSFET has 2-channel. So, MOSFET can be driven with more low impedance and losses. For low power inverter with MOSFET, the power losses of unified PWM are lower than that of unipolar and bipolar PWM. Proposed method and losses analysis results are verified by examination and simulation using Matlab/Simulink.

CPW 임피던스 변환회로를 이용한 광대역 마이크로파 SPDT 스위치 (Broadband Microwave SPDT Switch Using CPW Impedance Transform Network)

  • 이강호;박형무;이진구;구경헌
    • 대한전자공학회논문지TC
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    • 제42권7호
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    • pp.57-62
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    • 2005
  • 본 논문에서는 마이크로파 SPDT 스위치를 GaAs pHEMT 공정을 이용하여 설계 및 제작하였다. 광대역 스위치 설계를 위하여 CPW로 구현한 임피던스 변환회로를 삽입하여 온-저항과 오프-커패시턴스를 줄임으로서 낮은 삽입손실과 높은 격리도를 갖는 구조를 구현하였다. 변환회로를 구성하는 전송선로의 소자 개수와 병렬로 삽입되는 FET의 개수는 시물레이션을 통해 최적의 값으로 설계하였다. 설계된 스위치의 측정 결과 53$\~$ 61 GHz 대역에서 2.6 dB 이하의 삽입손실과 24 dB 이상의 격리도를 얻었다.

BLDC 모터의 PWM 방법과 파워소자에 따른 인버터 손실분석 (Analysis of Inverter Losses of Brushless DC Motor According to PWM Method and Power Devices)

  • 남명준;조관열;김학원;엄상준;김영진;김기만
    • 전력전자학회:학술대회논문집
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    • 전력전자학회 2014년도 추계학술대회 논문집
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    • pp.33-34
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    • 2014
  • In this paper, the inverter switch losses of BLDC motor for three types of PWM method and power devices was analyzed. When BLDC motor is driven at low currents, inverter switch losses for MOSFET is low because MOSFET operates like resistance. But, inverter switch losses for IGBT is higher than MOSFET due to its large turn-off losses. For low power inverter with MOSFET, the power losses of unified PWM is lower than that of unipolar and bipolar PWM.

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초전도 영구전류스위치의 설계. 제작 및 특성시험 (The design, construction and operational characteristics of the superconducting persistent current switch)

  • 오윤상;이상진;최경달;류강식;고태국
    • 대한전기학회논문지
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    • 제45권2호
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    • pp.193-198
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    • 1996
  • Low power superconducting persistent current switch(PCS) for the superconducting magnet systems in the persistent mode was developed and its experimental results were analyzed when the system was charged or discharged. The multifilament NbTi wire with Cu matrix was used for the PCS. The constructed NbTi superconducting switch with superconducting magnet system operated successfully. It also operated on-off switching action with good stabilization. The maximum operating current in persistent mode was 60A (at 1T). In persistent current mode, the decay of the persistent current at 60A was observed. Its decay was 3.55% in 60 min. It is possible to make the persistent current switch with the better decaying of persistent current if some problems for joint resistance are solved.

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프로그램 가능한 논리 회로 구성을 위한 PIP 앤티퓨즈의 전기적 특성 (Electrical Characteristics of the PIP Antifuse for Configuration of the Programmable Logic Circuit)

  • 김필중;윤중현;김종빈
    • 한국전기전자재료학회논문지
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    • 제14권12호
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    • pp.953-958
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    • 2001
  • The antifuse is a semi-permanent memory device like a ROM which shows the open or short state, and a switch device connecting logic blocks selectively in FPGA. In addition, the antifuse has been used as a logic device to troubleshoot defective memory cells arising from SDRAM processing. In this study, we have fabricated ONO antifuses consisted of PIP structure. The antifuse shows a high resistance more than several G Ω in the normal state, and shows a low resistance less than 500 Ω after program. The program resistance variation according to temperature shows the very stable value of $\pm$20 Ω. At this time, its program voltage shows 6.7∼7.2 V and the program is performed within 1 second. Therefore this result shows that the PIP antifuse is a very stable and programmable logic device.

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16 V 급 NMOSFET 소자의 낮은 게이트 전압 영역에서 출력저항 개선에 대한 연구 (Design and Analysis of 16 V N-TYPE MOSFET Transistor for the Output Resistance Improvement at Low Gate Bias)

  • 김영목;이한신;성만영
    • 한국전기전자재료학회논문지
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    • 제21권2호
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    • pp.104-110
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    • 2008
  • In this paper we proposed a new source-drain structure for N-type MOSFET which can suppress the output resistance reduction of a device in saturation region due to soft break down leakage at high drain voltage when the gate is biased around relatively low voltage. When a device is generally used as a switch at high gate bias the current level is very important for the operation. but in electronic circuit like an amplifier we should mainly consider the output resistance for the stable voltage gain and the operation at low gate bias. Hence with T-SUPREM simulator we designed devices that operate at low gate bias and high gate bias respectively without a extra photo mask layer and ion-implantation steps. As a result the soft break down leakage due to impact ionization is reduced remarkably and the output resistance increases about 3 times in the device that operates at the low gate bias. Also it is expected that electronic circuit designers can easily design a circuit using the offered N-type MOSFET device with the better output resistance.

High Efficiency Buck-Converter with Short Circuit Protection

  • Cho, Han-Hee;Park, Kyeong-Hyeon;Cho, Sang-Woon;Koo, Yong-Seo
    • IEIE Transactions on Smart Processing and Computing
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    • 제3권6호
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    • pp.425-429
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    • 2014
  • This paper proposes a DC-DC Buck-Converter with DT-CMOS (Dynamic Threshold-voltage MOSFET) Switch. The proposed circuit was evaluated and compared with a CMOS switch by both the circuit and device simulations. The DT-CMOS switch reduced the output ripple and the conduction loss through a low on-resistance. Overall, the proposed circuit showed excellent performance efficiency compared to the converter with conventional CMOS switch. The proposed circuit has switching frequency of 1.2MHz, 3.3V input voltage, 2.5V output voltage, and maximum current of 100mA. In addition, this paper proposes a SCP (Short Circuit Protection) circuit to ensure reliability.

A Non-isolated High Step-up DC/DC Converter with Low EMI and Voltage Stress for Renewable Energy Applications

  • Baharlou, Solmaz;Yazdani, Mohammad Rouhollah
    • Journal of Electrical Engineering and Technology
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    • 제12권3호
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    • pp.1187-1194
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    • 2017
  • In this paper, a high step-up DC-DC PWM converter with continuous input current and low voltage stress is presented for renewable energy application. The proposed converter is composed of a boost converter integrated with an auxiliary step-up circuit. The auxiliary circuit uses an additional coupled inductor and a balancing capacitor with voltage doubler and switching capacitor technique to achieve high step-up voltage gain with an appropriate switch duty cycle. The switched capacitors are charged in parallel and discharged in series by the coupled inductor, stacking on the output capacitor. In the proposed converter, the voltage stress on the main switch is clamped, so a low voltage switch with low ON resistance can be used to reduce the conduction loss which results in the efficiency improvement. A detailed discussion on the operating principle and steady-state analyses are presented in the paper. To justify the theoretical analysis, experimental results of a 200W 40/400V prototype is presented. In addition, the conducted electromagnetic emissions are measured which shows a good EMC performance.