• Title/Summary/Keyword: Low Mode

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Compact and Low Insertion Loss Dual-Mode Resonator and Its Applications for Switchable Filters (낮은 삽입손실을 갖는 소형 이중모드 공진기와 스위치 기능을 가진 여파기로의 응용)

  • 성영제;김보연;이건준;김영식
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.15 no.3
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    • pp.301-310
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    • 2004
  • In this paper, a compact dual-mode filter structure without coupling gaps is proposed. The novel design is achieved by embedding a pair of equal crossed slots and spur-lines. Without coupling gaps between feed lines and patch resonator, the new filter can provide low insertion loss. It is found that this design has wide coupling range for dual-mode operation. It means that these characteristics of the proposed filter can reduce uncertainty in fabrication. By using two PIN diodes mounted inside a pair of spur-lines, the proposed structure works as a switchable filter. Also, it has a size reduction of about 34.7 %, compared with conventional dual-mode filters.

Design and Control Strategy for Autonomous and Seamless Mode Transition of High Efficiency Bidirectional DC-DC Converter for ISG Systems (ISG 시스템용 고효율 양방향 DC-DC 컨버터의 설계 및 자율적이며 끊김없는 모드전환을 위한 제어전략)

  • Park, Jun-Sung;Kwon, Min-Ho;Choi, Se-Wan
    • The Transactions of the Korean Institute of Power Electronics
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    • v.21 no.1
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    • pp.19-26
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    • 2016
  • In this study, a bidirectional DC-DC converter for idle stop and go (ISG) is developed to reduce fuel consumption. A three-phase non-isolated half-bridge converter is selected through a design method by considering efficiency and volume. According to the state of charge of the batteries at both the low-voltage and high-voltage sides, buck mode, which charges a low-voltage battery from the generated motor energy, and boost mode, which provides power to the motor from the low- and high-voltage battery sides, are required in the ISG system. Hence, an autonomous and seamless bidirectional control method using a variable current limiter is proposed for mode change. A 1.8 kW engineering sample of the proposed converter has been built and tested to verify the validity of the proposed concept. The maximum efficiencies, including gate driver and control circuit losses, are 96.4% in charging mode and 96.1% in discharging mode.

Low Splicing Loss Technique between Standard Single Mode Fiber and High Δ Fiber (표준 단일모드 광섬유와 하이델타 광섬유사이의 저 손실 접속 기법)

  • Kim, Kwang-Taek;Yang, Byoung-Cheoul
    • Korean Journal of Optics and Photonics
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    • v.19 no.3
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    • pp.169-174
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    • 2008
  • In this paper, we have presented techniques to reduce the splicing loss between standard single mode fiber and high ${\Delta}$ single mode fiber based on the mode expanding and mode evolution induced by thermal treatment of the fibers. The experimental results show that mechanical splicing loss can be reduced from 2.3 dB to 0.1 dB through proper thermal treatment of the high ${\Delta}$ fiber. Meanwhile, we achieved $0.2{\sim}0.4dB$ of low splicing loss between two fibers by heating the splicing region using electric arcing or an oxygen flame.

Performance Evaluation of Ethernet Frame Burst Mode in EPON Downstream Link

  • Jia, Wen-Kang;Chen, Yaw-Chung
    • ETRI Journal
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    • v.30 no.2
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    • pp.290-300
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    • 2008
  • We apply IEEE 802.3 frame burst mode (FBM) to the Ethernet passive optical network (EPON) downstream link and compare its performance with non-frame burst mode for various traffic patterns. Although in light traffic loads (p<0.5) the efficiency of the FBM mechanism is not significant, it does feature high throughput, small jitter, low queue occupancy, and short queuing delay in optical line terminals under various traffic loads with various numbers of optical network units (ONUs). The FBM performance always approaches that of full-duplex mode, especially under heavy traffic loads (p>0.5). Moreover, an increase in number of ONUs will decrease the burst performance. Our work shows that FBM scheme is very useful for EPON transmission and has low design complexity.

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A Reduced-Swing Voltage-Mode Driver for Low-Power Multi-Gb/s Transmitters

  • Song, Hee-Soo;Kim, Su-Hwan;Jeong, Deog-Kyoon
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.9 no.2
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    • pp.104-109
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    • 2009
  • At a lower supply voltage, voltage-mode drivers draw less current than current-mode drivers. In this paper, we newly propose a voltage-mode driver with an additional current path that reduces the output voltage swing without the need for complicated additional circuitry, compared to conventional voltage-mode drivers. The prototype driver is fabriccated in a 0.13-$^{\mu}m$ CMOS technology and used to transmit data streams at the rate of 2.5 Gb/s. Deemphasis is also implemented for the compensation of channel attenuation. With a 1.2-V supply, it dissipates 8.0 mA for a 400-mV output voltage swing.

A Smooth LVRT Control Strategy for Single-Phase Two-Stage Grid-Connected PV Inverters

  • Xiao, Furong;Dong, Lei;Khahro, Shahnawaz Farhan;Huang, Xiaojiang;Liao, Xiaozhong
    • Journal of Power Electronics
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    • v.15 no.3
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    • pp.806-818
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    • 2015
  • Based on the inherent relationship between dc-bus voltage and grid feeding active power, two dc-bus voltage regulators with different references are adopted for a grid-connected PV inverter operating in both normal grid voltage mode and low grid voltage mode. In the proposed scheme, an additional dc-bus voltage regulator paralleled with maximum power point tracking controller is used to guarantee the reliability of the low voltage ride-through (LVRT) of the inverter. Unlike conventional LVRT strategies, the proposed strategy does not require detecting grid voltage sag fault in terms of realizing LVRT. Moreover, the developed method does not have switching operations. The proposed technique can also enhance the stability of a power system in case of varying environmental conditions during a low grid voltage period. The operation principle of the presented LVRT control strategy is presented in detail, together with the design guidelines for the key parameters. Finally, a 3 kW prototype is built to validate the feasibility of the proposed LVRT strategy.

CMI Tolerant Readout IC for Two-Electrode ECG Recording (공통-모드 간섭 (CMI)에 강인한 2-전극 기반 심전도 계측 회로)

  • Sanggyun Kang;Kyeongsik Nam;Hyoungho Ko
    • Journal of Sensor Science and Technology
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    • v.32 no.6
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    • pp.432-440
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    • 2023
  • This study introduces an efficient readout circuit designed for two-electrode electrocardiogram (ECG) recording, characterized by its low-noise and low-power consumption attributes. Unlike its three-electrode counterpart, the two-electrode ECG is susceptible to common-mode interference (CMI), causing signal distortion. To counter this, the proposed circuit integrates a common-mode charge pump (CMCP) with a window comparator, allowing for a CMI tolerance of up to 20 VPP. The CMCP design prevents the activation of electrostatic discharge (ESD) diodes and becomes operational only when CMI surpasses the predetermined range set by the window comparator. This ensures power efficiency and minimizes intermodulation distortion (IMD) arising from switching noise. To maintain ECG signal accuracy, the circuit employs a chopper-stabilized instrumentation amplifier (IA) for low-noise attributes, and to achieve high input impedance, it incorporates a floating high-pass filter (HPF) and a current-feedback instrumentation amplifier (CFIA). This comprehensive design integrates various components, including a QRS peak detector and serial peripheral interface (SPI), into a single 0.18-㎛ CMOS chip occupying 0.54 mm2. Experimental evaluations showed a 0.59 µVRMS noise level within a 1-100 Hz bandwidth and a power draw of 23.83 µW at 1.8 V.

Design of a Low-Power MOS Current-Mode Logic Circuit (저 전력 MOS 전류모드 논리회로 설계)

  • Kim, Jeong-Beom
    • The KIPS Transactions:PartA
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    • v.17A no.3
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    • pp.121-126
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    • 2010
  • This paper proposes a low-power MOS current-mode logic circuit with the low voltage swing technology and the high-threshold sleep-transistor. The sleep-transistor is used to high-threshold voltage PMOS transistor to minimize the leakage current. The $16{\times}16$ bit parallel multiplier is designed by the proposed circuit structure. Comparing with the conventional MOS current-model logic circuit, the circuit achieves the reduction of the power consumption in sleep mode by 1/104. The proposed circuit is achieved to reduce the power consumption by 11.7% and the power-delay-product by 15.1% compared with the conventional MOS current-model logic circuit in the normal mode. This circuit is designed with Samsung $0.18\;{\mu}m$ standard CMOS process. The validity and effectiveness are verified through the HSPICE simulation.

Effects of Heat Losses on Edge-flame Instabilities in Low Strain Rate Counterflow Diffusion Flames (저신장율 대향류확산화염에서 에지화염 불안정성에 관한 열손실 효과)

  • Park June-Sung;Hwang Dong-Jin;Kim Jeong-Soo;Keel Sang-In;Kim Tae-Kwon;Park Jeong
    • Transactions of the Korean Society of Mechanical Engineers B
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    • v.30 no.10 s.253
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    • pp.996-1002
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    • 2006
  • Experiments in methane-air low strain rate counterflow diffusion flames diluted with nitrogen have been conducted to study the behavior of flame extinction and edge flame oscillation in which flame length is less than the burner diameter and thus lateral conduction heat loss in addition to radiative heat loss could be remarkable at low global strain rates. Critical mole fraction at flame extinction is examined with velocity ratio and global strain rate. Onset conditions of edge flame oscillation and flame oscillation modes are also provided with global strain rate and added nitrogen mole fraction to fuel stream (fuel Lewis number). It is seen that flame length is closely relevant to lateral heat loss, and this affects flame extinction and edge flame oscillation considerably. Edge flame oscillations in low strain rate flames are experimentally described well and are categorized into three: a growing oscillation mode, a decaying oscillation mode, and a harmonic oscillation mode. The regime of flame oscillation is also provided at low strain rate flames. Important contribution of lateral heat loss even to edge flame oscillation is clarified

The Study of Failure Mode Data Development and Feature Parameter's Reliability Verification Using LSTM Algorithm for 2-Stroke Low Speed Engine for Ship's Propulsion (선박 추진용 2행정 저속엔진의 고장모드 데이터 개발 및 LSTM 알고리즘을 활용한 특성인자 신뢰성 검증연구)

  • Jae-Cheul Park;Hyuk-Chan Kwon;Chul-Hwan Kim;Hwa-Sup Jang
    • Journal of the Society of Naval Architects of Korea
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    • v.60 no.2
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    • pp.95-109
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    • 2023
  • In the 4th industrial revolution, changes in the technological paradigm have had a direct impact on the maintenance system of ships. The 2-stroke low speed engine system integrates with the core equipment required for propulsive power. The Condition Based Management (CBM) is defined as a technology that predictive maintenance methods in existing calender-based or running time based maintenance systems by monitoring the condition of machinery and diagnosis/prognosis failures. In this study, we have established a framework for CBM technology development on our own, and are engaged in engineering-based failure analysis, data development and management, data feature analysis and pre-processing, and verified the reliability of failure mode DB using LSTM algorithms. We developed various simulated failure mode scenarios for 2-stroke low speed engine and researched to produce data on onshore basis test_beds. The analysis and pre-processing of normal and abnormal status data acquired through failure mode simulation experiment used various Exploratory Data Analysis (EDA) techniques to feature extract not only data on the performance and efficiency of 2-stroke low speed engine but also key feature data using multivariate statistical analysis. In addition, by developing an LSTM classification algorithm, we tried to verify the reliability of various failure mode data with time-series characteristics.