DOI QR코드

DOI QR Code

A Reduced-Swing Voltage-Mode Driver for Low-Power Multi-Gb/s Transmitters

  • Song, Hee-Soo (School of Electrical Engineering, Seoul National University) ;
  • Kim, Su-Hwan (School of Electrical Engineering, Seoul National University) ;
  • Jeong, Deog-Kyoon (School of Electrical Engineering, Seoul National University)
  • Published : 2009.06.30

Abstract

At a lower supply voltage, voltage-mode drivers draw less current than current-mode drivers. In this paper, we newly propose a voltage-mode driver with an additional current path that reduces the output voltage swing without the need for complicated additional circuitry, compared to conventional voltage-mode drivers. The prototype driver is fabriccated in a 0.13-$^{\mu}m$ CMOS technology and used to transmit data streams at the rate of 2.5 Gb/s. Deemphasis is also implemented for the compensation of channel attenuation. With a 1.2-V supply, it dissipates 8.0 mA for a 400-mV output voltage swing.

Keywords

References

  1. M.-J. E. Lee, W. J. Dally, and P. Chiang, "Low-power area-efficient high-speed I/O circuit techniques," IEEE Journal of Solid-State Circuits, vol. 35, pp. 1591-1599, Nov. 2000 https://doi.org/10.1109/4.881204
  2. F. Yang, J. H. O'Neill, D. Inglis, and J. Othmer, "A CMOS low-power multiple 2.5-3.125-Gb/s serial link macrocell for high IO bandwidth network ICs", IEEE Journal of Solid-State Circuits, vol. 37, pp. 1813-1821, Dec. 2002 https://doi.org/10.1109/JSSC.2002.804341
  3. M. Green and U. Singh, "Design of CMOS CML circuits for high-speed broadband communications", IEEE International Symposium on Circuits and Systems, pp. 204-207, May 2003
  4. J. Cao, M. Green, A. Momtaz, K. Vakilian, D. Chung, K. Jen, M. Caresosa, X. Wang, W.-G. Tan, Y. Cai, I. Fujimori, and A. Hairapetian, "OC-192 transmitter and receiver in standard 0.18-μm CMOS", IEEE Journal of Solid-State Circuits, vol. 37, pp. 1768-1780, Dec. 2002 https://doi.org/10.1109/JSSC.2002.804336
  5. S. Sidiropoulos and M. Horowitz, "A 700-Mb/s/pin CMOS signaling interface using current integrating receivers," IEEE Journal of Solid-State Circuits, vol. 32, pp. 681-690, May 1997 https://doi.org/10.1109/4.568834
  6. K.-L. J. Wong, H. Hatamkhani, M. Mansuri, and C.-K. K. Yang., "A 27-mW 3.6-Gb/s I/O transceiver," IEEE Journal of Solid-State Circuits, vol. 39, pp. 602-612, Apr. 2004 https://doi.org/10.1109/JSSC.2004.825259
  7. J. Poulton, R. Palmer, A. M. Fuller, T. Greer, J. Eyles, W. J. Dally, and M. Horowitz, "A 14-mW 6.25-Gb/s transceiver in 90-nm CMOS," IEEE Journal of Solid-State Circuits, vol. 42, pp. 2745-2757, Dec. 2007 https://doi.org/10.1109/JSSC.2007.908692
  8. W.-J. Choe, B.-J. Lee, J. Kim, D.-K. Jeong, and G. Kim, "A 3-mW, 270-Mbps, clock-edge modulated serial link for mobile displays," IEEE Journal of Solid-State Circuits, vol. 42, pp. 2012-2020, Sept. 2007 https://doi.org/10.1109/JSSC.2007.903038
  9. H. Lu, H. Wang, C. Su, and C.-N. J. Liu, "Design of an all-digital LVDS driver," IEEE Transaction on Circuits and Systems I: Regular Papers, to be published https://doi.org/10.1109/TCSI.2008.2008279

Cited by

  1. voltage-mode driver with independently matched pull-up and pull-down impedances vol.43, pp.12, 2014, https://doi.org/10.1002/cta.2050
  2. A Tunable Swing-Reduced Driver in 0.13-μm MTCMOS Technology vol.26, pp.11, 2017, https://doi.org/10.1142/S0218126617501821