1 |
J. Cao, M. Green, A. Momtaz, K. Vakilian, D. Chung, K. Jen, M. Caresosa, X. Wang, W.-G. Tan, Y. Cai, I. Fujimori, and A. Hairapetian, "OC-192 transmitter and receiver in standard 0.18-μm CMOS", IEEE Journal of Solid-State Circuits, vol. 37, pp. 1768-1780, Dec. 2002
DOI
ScienceOn
|
2 |
K.-L. J. Wong, H. Hatamkhani, M. Mansuri, and C.-K. K. Yang., "A 27-mW 3.6-Gb/s I/O transceiver," IEEE Journal of Solid-State Circuits, vol. 39, pp. 602-612, Apr. 2004
DOI
ScienceOn
|
3 |
H. Lu, H. Wang, C. Su, and C.-N. J. Liu, "Design of an all-digital LVDS driver," IEEE Transaction on Circuits and Systems I: Regular Papers, to be published
DOI
ScienceOn
|
4 |
S. Sidiropoulos and M. Horowitz, "A 700-Mb/s/pin CMOS signaling interface using current integrating receivers," IEEE Journal of Solid-State Circuits, vol. 32, pp. 681-690, May 1997
DOI
ScienceOn
|
5 |
W.-J. Choe, B.-J. Lee, J. Kim, D.-K. Jeong, and G. Kim, "A 3-mW, 270-Mbps, clock-edge modulated serial link for mobile displays," IEEE Journal of Solid-State Circuits, vol. 42, pp. 2012-2020, Sept. 2007
DOI
ScienceOn
|
6 |
J. Poulton, R. Palmer, A. M. Fuller, T. Greer, J. Eyles, W. J. Dally, and M. Horowitz, "A 14-mW 6.25-Gb/s transceiver in 90-nm CMOS," IEEE Journal of Solid-State Circuits, vol. 42, pp. 2745-2757, Dec. 2007
DOI
ScienceOn
|
7 |
F. Yang, J. H. O'Neill, D. Inglis, and J. Othmer, "A CMOS low-power multiple 2.5-3.125-Gb/s serial link macrocell for high IO bandwidth network ICs", IEEE Journal of Solid-State Circuits, vol. 37, pp. 1813-1821, Dec. 2002
DOI
ScienceOn
|
8 |
M. Green and U. Singh, "Design of CMOS CML circuits for high-speed broadband communications", IEEE International Symposium on Circuits and Systems, pp. 204-207, May 2003
|
9 |
M.-J. E. Lee, W. J. Dally, and P. Chiang, "Low-power area-efficient high-speed I/O circuit techniques," IEEE Journal of Solid-State Circuits, vol. 35, pp. 1591-1599, Nov. 2000
DOI
ScienceOn
|