• Title/Summary/Keyword: Low Density Parity Check

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Structured LDPC Codes for Mobile Multimedia Communication Systems (이동 멀티미디어 통신 시스템을 위한 구조적인 저밀도패리티검사 부호)

  • Yu, Seog-Kun;Joo, Eon-Kyeong
    • Journal of the Institute of Electronics Engineers of Korea SC
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    • v.48 no.2
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    • pp.35-39
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    • 2011
  • Error correcting codes with easy variability in code rate and codeword length in addition to powerful error correcting capability are required for present and future mobile multimedia communication systems. And low complexity is also needed for the compact mobile terminals. In general, the irregular random LDPC(low-density parity-check) code is known to have the superior performance among various LDPC codes. But it has inefficiency since the various parity check matrices for various services should be stored for encoding and decoding. The structured LDPC codes which can easily provide various rates and lengths are studied recently. Therefore, the flexibility, memory size, and error performance of various structured LDPC codes are compared and analyzed in this paper. And the most appropriate structured LDPC code is also suggested.

Efficient Partial Parallel Encoders for IRA Codes in DVB-S2 (DVB-S2 IRA Code를 위한 최적 부호화 방법)

  • Hwang, Sung-Oh;Lee, Jai-Yong
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.35 no.11C
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    • pp.901-906
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    • 2010
  • Low density parity check (LDPC) code, first introduced by Gallager and re-discovered by MacKay et al, has attracted researcher's interest mainly due to their performance and low decoding complexity. It was remarkable that the performance is very close to Shannon capacity limit under the assumption of having long codeword length and iterative decoder. However, comparing to turbo codes widely used in the current mobile communication, the encoding complexity of LDPC codes has been regarded as the drawback. This paper proposes a solution for DVB-S2 LDPC encoder to reduce the encoder latency. We use the fast IRA encoder that use the transformation of the parity check matrix into block-wise form and the partial parallel process to reduce the number of system clocks for the IRA code encoding. We compare the proposed encoder with the current DVB-S2 encoder to show that the performance of proposal is better than that of the current DVB-S2 encoder.

Early Stop Algorithm using the Parity Check Method for LDPC Decoders Based on IRIG 106 Standards (Parity Check 방식을 이용한 IRIG 106 표준 기반 LDPC 복호기의 조기 종료 알고리즘)

  • Jae-Hun Lee;Hyun-Woo Jeong;Ye-Gwon Hong;Ji-Won Jung
    • The Journal of Korea Institute of Information, Electronics, and Communication Technology
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    • v.17 no.4
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    • pp.198-204
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    • 2024
  • LDPC, known for its excellent error correction capability, has been adopted as the channel coding technique in the IRIG 106 standard, which is standard for data transmission methods in the aerospace field. Iterative codes such as LDPC require large block sizes and number of iterations in order to improve performance. However, large number of iterations induce computational complexity and power consumption. To solve these problems, this paper presents a parity check-based early stop algorithm that reduces the average number of iterations while maintaining the same performance. BER performance and iteration reduction amounts are compared between early stop algorithm and conventional method that has fixed number of iterations for various coding rate and information bit size defined in the IRIG 106 standard. Through simulation results, we confirmed required iteration numbers are reduced about 50% above without performance loss.

Analysis of error correction capability and recording density of an optical disc system with LDPC code (LDPC 코드를 적용한 광 디스크 시스템의 에러 정정 성능 및 기록 용량 분석)

  • 김기현;김현정;이윤우
    • Proceedings of the IEEK Conference
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    • 2003.11a
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    • pp.537-540
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    • 2003
  • In this paper, we evaluated error correction performance and recording density of an optical disc system. The performance of Low-Density Parity Check code (LDPC) is compared to the HD-DVD (BD) ECC. The recording density of optical disc can be increased by reducing the redundancy of the user data. Moreover, since the correction capability of LDPC with decreased redundancy is better than that of BD, the recording density can also be increased by reducing the mark length of the data on the disc surface.

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Iterative Reliability-Based Modified Majority-Logic Decoding for Structured Binary LDPC Codes

  • Chen, Haiqiang;Luo, Lingshan;Sun, Youming;Li, Xiangcheng;Wan, Haibin;Luo, Liping;Qin, Tuanfa
    • Journal of Communications and Networks
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    • v.17 no.4
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    • pp.339-345
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    • 2015
  • In this paper, we present an iterative reliability-based modified majority-logic decoding algorithm for two classes of structured low-density parity-check codes. Different from the conventional modified one-step majority-logic decoding algorithms, we design a turbo-like iterative strategy to recover the performance degradation caused by the simply flipping operation. The main computational loads of the presented algorithm include only binary logic and integer operations, resulting in low decoding complexity. Furthermore, by introducing the iterative set, a very small proportion (less than 6%) of variable nodes are involved in the reliability updating process, which can further reduce the computational complexity. Simulation results show that, combined with the factor correction technique and a well-designed non-uniform quantization scheme, the presented algorithm can achieve a significant performance improvement and a fast decoding speed, even with very small quantization levels (3-4 bits resolution). The presented algorithm provides a candidate for trade-offs between performance and complexity.

Novel Class of Entanglement-Assisted Quantum Codes with Minimal Ebits

  • Dong, Cao;Yaoliang, Song
    • Journal of Communications and Networks
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    • v.15 no.2
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    • pp.217-221
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    • 2013
  • Quantum low-density parity-check (LDPC) codes based on the Calderbank-Shor-Steane construction have low encoding and decoding complexity. The sum-product algorithm(SPA) can be used to decode quantum LDPC codes; however, the decoding performance may be significantly decreased by the many four-cycles required by this type of quantum codes. All four-cycles can be eliminated using the entanglement-assisted formalism with maximally entangled states (ebits). The proposed entanglement-assisted quantum error-correcting code based on Euclidean geometry outperform differently structured quantum codes. However, the large number of ebits required to construct the entanglement-assisted formalism is a substantial obstacle to practical application. In this paper, we propose a novel class of entanglement-assisted quantum LDPC codes constructed using classical Euclidean geometry LDPC codes. Notably, the new codes require one copy of the ebit. Furthermore, we propose a construction scheme for a corresponding zigzag matrix and show that the algebraic structure of the codes could easily be expanded. A large class of quantum codes with various code lengths and code rates can be constructed. Our methods significantly improve the possibility of practical implementation of quantum error-correcting codes. Simulation results show that the entanglement-assisted quantum LDPC codes described in this study perform very well over a depolarizing channel with iterative decoding based on the SPA and that these codes outperform other quantum codes based on Euclidean geometries.

Development of A Recovery Algorithm for Sparse Signals based on Probabilistic Decoding (확률적 희소 신호 복원 알고리즘 개발)

  • Seong, Jin-Taek
    • The Journal of Korea Institute of Information, Electronics, and Communication Technology
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    • v.10 no.5
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    • pp.409-416
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    • 2017
  • In this paper, we consider a framework of compressed sensing over finite fields. One measurement sample is obtained by an inner product of a row of a sensing matrix and a sparse signal vector. A recovery algorithm proposed in this study for sparse signals based probabilistic decoding is used to find a solution of compressed sensing. Until now compressed sensing theory has dealt with real-valued or complex-valued systems, but for the processing of the original real or complex signals, the loss of the information occurs from the discretization. The motivation of this work can be found in efforts to solve inverse problems for discrete signals. The framework proposed in this paper uses a parity-check matrix of low-density parity-check (LDPC) codes developed in coding theory as a sensing matrix. We develop a stochastic algorithm to reconstruct sparse signals over finite field. Unlike LDPC decoding, which is published in existing coding theory, we design an iterative algorithm using probability distribution of sparse signals. Through the proposed recovery algorithm, we achieve better reconstruction performance as the size of finite fields increases. Since the sensing matrix of compressed sensing shows good performance even in the low density matrix such as the parity-check matrix, it is expected to be actively used in applications considering discrete signals.

Architecture of an LDPC Decoder for DVB-S2 using reuse Technique of processing units and Memory Relocation (연산기와 메모리 재사용을 이용한 효율적인 DVB-S2 규격의 LDPC 복호기 구조)

  • Park Jae-Geun;Lee Chan-Ho
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.43 no.9 s.351
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    • pp.31-37
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    • 2006
  • Low-density parity-check (LDPC) codes are recently emerged due to its excellent performance. The standard for European high definition satellite digital video broadcast, DVB-S2 has adopted LDPC codes as a channel coding scheme. This paper proposes a DVB-S2 LDPC decoder architecture using a hybrid parity check matrix which is efficient in hardware implementation for both decoders and encoders. The hybrid H-matrices are constructed so that both the semi-random technique and the partly parallel structure can be applied to design encoders and decoders. Using the hybrid H-matrix scheme, the architecture of LDPC decoder for DVB-S2 can be very practical and efficient. In addition, we show a new Variable Node processor Unit (VNU) architecture to reuse the VNU for various code rates and optimized block memory placement to reuse. We design a DVB-S2 LDPC decoder of code rate 1/2 usng the proposed architecture. We estimate the performance of the DVB-S2 LDPC decoder and compare it with other decoders.

An analysis of the effects of LLR approximation on LDPC decoder performance (LLR 근사화에 따른 LDPC 디코더의 성능 분석)

  • Na, Yeong-Heon;Jeong, Sang-Hyeok;Shin, Kyung-Wook
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2009.10a
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    • pp.405-409
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    • 2009
  • In this paper, the effects of LLR (Log-Likelihood Ratio) approximation on LDPC (Low-Density Parity-Check) decoder performance are analyzed, and optimal design conditions of LDPC decoder are derived. The min-sum LDPC decoding algorithm which is based on an approximation of LLR sum-product algorithm is modeled and simulated by MATLAB, and it is analyzed that the effects of LLR approximation bit-width and maximum iteration cycles on the bit error rate (BER) performance of LDCP decoder. The parity check matrix for IEEE 802.11n standard which has block length of 1,944 bits and code rate of 1/2 is used, and AWGN channel with QPSK modulation is assumed. The simulation results show that optimal BER performance is achieved for 7 iteration cycles and LLR bit-width of (7,5).

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