• Journal of Communications and Networks
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• v.17 no.2
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• pp.157-161
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• 2015

A new block low-density parity-check (Block-LDPC) code based on quadratic permutation polynomials (QPPs) is proposed. The parity-check matrix of the Block-LDPC code is composed of a group of permutation submatrices that correspond to QPPs. The scheme provides a large range of implementable LDPC codes. Indeed, the most popular quasi-cyclic LDPC (QC-LDPC) codes are just a subset of this scheme. Simulation results indicate that the proposed scheme can offer similar error performance and implementation complexity as the popular QC-LDPC codes.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2010.05a
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• pp.798-801
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• 2010

This paper describes an efficient architecture for LDPC(Low-Density Parity Check) decoder, which supports three block lengths (648, 1,296, 1,944) of IEEE 802.11n standard. To minimize hardware complexity, the min-sum algorithm and block-serial layered structure are adopted in DFU(Decoding Function Unit) which is a main functional block in LDPC decoder. The optimized H-ROM structure for multi block lengths reduces the ROM size by 42% as compared to the conventional method. Also, pipelined memory read/write scheme for inter-layer DFU operations is proposed for an optimized operation of LDPC decoder.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.12C
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• pp.1143-1149
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• 2006

In this paper, the modified iterative decoding algorithm[8] by partitioning check nodes is applied to low-density parity-check(LDPC) codes in IEEE 802.16e standards, which gives us the improvement for convergence speed of decoding. Also, the new method of check node partitioning which is suitable for decoding of the LDPC codes in IEEE 802.16e system is proposed. The improvement of convergence speed in decoding reduces the number of iterations and thus the computational complexity of the decoder. The decoding method by partitioning check nodes can be applied to the LDPC codes whose decoder cannot be implemented in the fully parallel processing as an efficient sequential processing method. The modified iterative decoding method of LDPC codes using the proposed check node partitioning method can be used to implement the practical decoder in the wireless communication systems.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.37A no.11
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• pp.972-978
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• 2012

LDPC (low density parity check) code shows near Shannon limit performance by iterative decoding based on sum-product algorithm (SPA). Message updating procedure between variable and check nodes in SPA is done by a scheduling method. LDPC code shows different performance according to scheduling schemes. The conventional researches have been shown that the shuffled BP (belief propagation) algorithm shows better performance than the standard BP algorithm although it needs less number of iterations. However the reason is not analyzed clearly. Therefore the reason of difference in performance according to LDPC decoding algorithms is analyzed in this paper. 4 cases according to satisfaction of parity check condition are considered and compared. As results, the difference in the updating procedure in a cycle in the parity check matrix is considered to be the main reason of performance difference.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.38C no.10
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• pp.852-857
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• 2013

In this paper we propose a design algorithm for nonbinary LDPC (low-density parity-check) codes with low error-floors. The proposed algorithm determines the nonbinary values of the nonzero entries in the parity-check matrix in order to maximize the binary minimum distance of the designed nonbinary LDPC codes. We verify the performance of the designed nonbinary LDPC codes in the error-floor region by Monte Carlo simulation and importance sampling over BPSK (binary phase-shift keying) modulation.

• Proceedings of the KIEE Conference
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• 2006.07d
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• pp.2023-2024
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• 2006

1962년 Gallager에 의해 처음 제안된 LDPC 부호는 복호를 수행하는 부호방식으로 패리티 행렬(H)의 대부분이 0으로 구성되어 복호시에 적은 연산량을 요구하며, shannon의 한계에 도달하는 복호 능력으로, 차세대 통신의 주된 부호 방식으로 고려되고 있다. 하지만, LDPC는 부호화에 있어서 여타 다른 부호방식에 비해 복잡한 특성을 가지고 있으므로, 이를 개선하기 위한 부호방식의 적용이 필요하다. 본 논문에서는 효율 적인 부호화를 위하여 Dual-diagonal H parity행렬을 구성 하고, 쉽게 부호 길이를 확장 할 수 있는 Quasi-Cyclic 방식을 적용한 복호기를 구현하였다.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.44 no.3
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• pp.68-73
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• 2007

Recently, WSN(wireless sensor networks) consists of several sensor nodes in sensor field. And each sensors have the enforced energy constraint. Therefore, it is important to manage energy efficiently. In WSN application system, FEC(Forward error correction) increases the energy efficiency and data reliability of the data transmission. LDPC(Low density parity check) code is one of the FEC code. It needs more encoding operation than other FEC code by growing codeword length. But this code can approach the Shannon capacity limit and it is also can be used to increase the data reliability and decrease the transmission energy. In this paper, the author adopt Linear-Congruence method at generating parity check matrix of LDPC(Low density parity check) codes to reduce the complexity of encoding process and to enhance the energy efficiency in the WSN. As a result, the proposed algorithm can increase the encoding energy efficiency and the data reliability.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.11
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• pp.92-100
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• 2009

In this paper, we analyze the hardware architecture of Low Density Parity Check (LDPC) decoder using Log Likelihood Ration-Belief Propagation (LLR-BP) decoding algorithm. Various design issues that affect the decoding performance and the hardware complexity are discussed and the tradeoffs between the hardware complexity and the performance are analyzed. The message data for passing error probability is quantized to 7 bits and among them the fractional part is 4 bits. To maintain the decoding performance, the integer and fractional parts for the intrinsic information is 2 bits and 4 bits respectively. We discuss the alternate implementation of $\Psi$(x) function using piecewise linear approximation. Also, we improve the hardware complexity and the decoding time by applying overlapped scheduling.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.1
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• pp.8-14
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• 2013

A low density parity check (LDPC) decoder provides a most powerful error control capability for mobile communication devices and storage systems, due to its performance being close to Shannon's limit. In this paper, we introduce an efficient overlapped LDPC decoding algorithm using a upper dual-diagonal parity check matrix structure. By means of this algorithm, the LDPC decoder can concurrently execute parts of the check node update and variable node update in the sum-product algorithm. In this way, we can reduce the number of clock cycles per iteration as well as reduce the total latency. The proposed decoding structure offers a very simple control and is very flexible in terms of the variable bit length and variable code rate. The experiment results show that the proposed decoder can complete the decoding of codewords within 70% of the number of clock cycles required for a conventional non-overlapped decoder. The proposed design also reduces the power consumption by 33% when compared to the non-overlapped design.

• Journal of Broadcast Engineering
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• v.25 no.1
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• pp.36-47
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• 2020

The improved belief-propagation-based algorithms, such as normalized min-sum algorithm (NMSA) or offset min-sum algorithm (OMSA), are widely used to decode LDPC(Low-Density Parity-Check) codes because they are less computationally complex and work well even at low SNR(Signal-to-Noise Ratio). However, these algorithms work well only when an appropriate normalization factor or offset value is used. A new method that uses a CMD(Check Node Message Distribution) chart and least-square method, which has been recently proposed, has advantages on computational complexity over other approaches to get optimal coefficients. Furthermore, this method can be used to derive coefficients for each iteration. In this paper, we apply this method and propose an algorithm to derive a combination of normalization factor and offset value for a combined normalized and offset min-sum algorithm to further improve the decoding of LDPC codes. Simulations on the next-generation broadcasting standards, ATSC 3.0 LDPC codes, prove that a combined normalized and offset min-sum algorithm which takes the proposed coefficients as correction coefficients shows the best BER performance among other decoding algorithms.