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  • Title/Summary/Keyword: Low Density Parity Check

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Performance Comparison of LDPC codes with Different Soft-output Algorithm for High Density Optical Recording Channel (고밀도 광 기록 채널에서 LDPC 부호의 연판정 출력 알고리즘별 성능비교)

  • Lee, Bong-Il;Lee, Jae-Jin
    • Proceedings of the IEEK Conference
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    • 2008.06a
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    • pp.891-892
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    • 2008
  • 본 논문에서는 최근 주목받고 있는 에러 정정 기법 중 하나인 LDPC(Low Density Parity Check) 부호를 광 기록 채널(Optical Recording Channel)에 적용해 보았고 이때 사용되는 연판정 출력 알고리즘으로 MAP과 SOVA를 이용하여 성능을 비교하였다.

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New Min-sum LDPC Decoding Algorithm Using SNR-Considered Adaptive Scaling Factors

  • Jung, Yongmin;Jung, Yunho;Lee, Seongjoo;Kim, Jaeseok
    • ETRI Journal
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    • v.36 no.4
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    • pp.591-598
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    • 2014
  • This paper proposes a new min-sum algorithm for low-density parity-check decoding. In this paper, we first define the negative and positive effects of the received signal-to-noise ratio (SNR) in the min-sum decoding algorithm. To improve the performance of error correction by considering the negative and positive effects of the received SNR, the proposed algorithm applies adaptive scaling factors not only to extrinsic information but also to a received log-likelihood ratio. We also propose a combined variable and check node architecture to realize the proposed algorithm with low complexity. The simulation results show that the proposed algorithm achieves up to 0.4 dB coding gain with low complexity compared to existing min-sum-based algorithms.

Design of High Speed LDPC Encoder Based on DVB-S2 Standard (DVB-S2 기반 고속 LDPC 부호기 설계)

  • Park, Gun Yeol;Lee, Seong Ro;Jeon, Sung Min;Jung, Ji-Won
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.38C no.2
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    • pp.196-201
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    • 2013
  • In this paper, we proposed high speed LDPC encoder architecture for DVB-S2 standard. In conventional algorithm, the processes of parity calculations are serial fashion. Therefore conventional algorithm need clocks of number of parity. The proposed LDPC encoding architecture is based on a parallel 360 bits-wise operations. The key issues for realizing high speed are using the two kinds of index addresses and make use of memories efficiently. We implemented a half rate LDPC encoder on an FPGA, and confirmed its maximum throughput is up to 10 Gbps on 100MHz clock.

Analysis a LDPC code in the VDSL system (VDSL 시스템에서의 LDPC 코드 연구)

  • Joh, Kyung-Hyun;Kang, Hee-Hoon;Yi, Sang-Hoi;Na, Kuk-Hwan
    • Proceedings of the IEEK Conference
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    • 2006.06a
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    • pp.999-1000
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    • 2006
  • The LDPC Code is focusing a powerful FEC(Forward Error Correction) codes for 4G Mobile Communication system. LDPC codes are used minimizing channel errors by modeling AWGN Channel as VDSL system. The performance of LDPC code is better than that of turbo code in long code word on iterative decoding algorithm. LDPC code are encoded by sparse parity check matrix. there are decoding algorithms for a LDPC code, Bit Flipping, Message passing, Sum-Product. Because LDPC Codes use low density parity bit, mathematical complexity is low and relating processing time becomes shorten.

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A Memory-efficient Partially Parallel LDPC Decoder for CMMB Standard (메모리 사용을 최적화한 부분 병렬화 구조의 CMMB 표준 지원 LDPC 복호기 설계)

  • Park, Joo-Yul;Lee, So-Jin;Chung, Ki-Seok;Cho, Seong-Min;Ha, Jin-Seok;Song, Yong-Ho
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.48 no.1
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    • pp.22-30
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    • 2011
  • In this paper, we propose a memory efficient multi-rate Low Density Parity Check (LDPC) decoder for China Mobile Multimedia Broadcasting (CMMB). We find the best trade-off between the performance and the circuit area by designing a partially parallel decoder which is capable of passing multiple messages in parallel. By designing an efficient address generation unit (AGU) with an index matrix, we could reduce both the amount of memory requirement and the complexity of computation. The proposed regular LDPC decoder was designed in Verilog HDL and was synthesized by Synopsys' Design Compiler using Chartered 0.18μm CMOS cell library. The synthesized design has the gate size of 455K (in NAND2). For the two code rates supported by CMMB, the rate-1/2 decoder has a throughput of 14.32 Mbps, and the rate-3/4 decoder has a throughput of 26.97 Mbps. Compared with a conventional LDPC for CMMB, our proposed design requires only 0.39% of the memory.

Low Complexity Iterative Detection and Decoding using an Adaptive Early Termination Scheme in MIMO system (다중 안테나 시스템에서 적응적 조기 종료를 이용한 낮은 복잡도 반복 검출 및 복호기)

  • Joung, Hyun-Sung;Choi, Kyung-Jun;Kim, Kyung-Jun;Kim, Kwang-Soon
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.36 no.8C
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    • pp.522-528
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    • 2011
  • The iterative detection and decoding (IDD) has been shown to dramatically improve the bit error rate (BER) performance of the multiple-input multiple-output (MIMO) communication systems. However, these techniques require a high computational complexity since it is required to compute the soft decisions for each bit. In this paper, we show IDD comprised of sphere decoder with low-density parity check (LDPC) codes and present the tree search strategy, called a layer symbol search (LSS), to obtain soft decisions with a low computational complexity. In addition, an adaptive early termination is proposed to reduce the computational complexity during an iteration between an inner sphere decoder and an outer LDPC decoder. It is shown that the proposed approach can achieve the performance similar to an existing algorithm with 70% lower computational complexity compared to the conventional algorithms.

Performance Of Iterative Decoding Schemes As Various Channel Bit-Densities On The Perpendicular Magnetic Recording Channel (수직자기기록 채널에서 기록 밀도에 따른 반복복호 기법의 성능)

  • Park, Dong-Hyuk;Lee, Jae-Jin
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.35 no.7C
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    • pp.611-617
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    • 2010
  • In this paper, we investigate the performances of the serial concatenated convolutional codes (SCCC) and low-density parity-check (LDPC) codes on perpendicular magnetic recording (PMR) channels. We discuss the performance of two systems when user bit-densities are 1.7, 2.0, 2.4 and 2.8, respectively. The SCCC system is less complex than LDPC system. The SCCC system consists of recursive systematic convolutional (RSC) codes encoder/decoder, precoder and random interleaver. The decoding algorithm of the SCCC system is the soft message-passing algorithm and the decoding algorithm of the LDPC system is the log domain sum-product algorithm (SPA). When we apply the iterative decoding between channel detector and the error control codes (ECC) decoder, the SCCC system is compatible with the LDPC system even at the high user bit density.

LDPC Coding for image data and FPGA Implementation of LDPC Decoder (영상 정보의 LDPC 부호화 및 복호기의 FPGA구현)

  • Jang, Eun-Young
    • The Journal of the Korea institute of electronic communication sciences
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    • v.12 no.4
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    • pp.569-574
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    • 2017
  • In order to transmit information in a channel environment in which noise exists, a coding technique of information is required. One of the coding techniques used for error detection and correction close to the Shannon limit is Low Density Parity Code(LDPC). LDPC and decoding characteristic features by Sum-product algorithm are matched for the performance to Turbo Code, RA(Repeat Accumulate) code, in case of very long code length of LDPC surpass their performance. This paper explains LDPC coding scheme of image data and decoding scheme, implements LDPC decoder in FPGA.

Evaluation of soft iterative decoder with run length limited code in optical storage system

  • 김기현;한성휴;심재성;박현수;박인식
    • Proceedings of the IEEK Conference
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    • 2002.06e
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    • pp.99-102
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    • 2002
  • In this work, we evaluated the performance of soft iterative decoder with soft block decoder in optical storage system. Because optical storage system requires run- length limited code in general, adaptation of the soft decoders such as turbo code or LDPC(low density parity check code) is difficult without soft block decoders. The performance of the overall optical detection system is evaluated and the simplified channel detection is also proposed.

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Serially Concatenated Space-Time LDPC Codes for High Data Rate Wireless Communication (고속 무선 통신을 위한 직렬 연접 시공간 LDPC 부호에 관한 연구)

  • 장혜경;이문호
    • Proceedings of the IEEK Conference
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    • 2002.06a
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    • pp.335-338
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    • 2002
  • For high data rate transmission over wireless fading channels, space-time trellis ceding techniques can be employed to increase the Information capacity of the communication system dramatically. In this paper, we consider the concatenated space time LDPC (Low Density Parity Check) codes. Extra ceding gains In addition to the diversity advantage is shown to be achieved for certain space-time trellis codes transmitted over quasi-static lading channels.

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