• Journal of Computing Science and Engineering
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• v.6 no.4
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• pp.310-319
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• 2012

Next generation wireless receivers demand low computational complexity algorithms with high computing power in order to perform fast signal detections and error estimations. Several signal detection and estimation algorithms have been proposed for next generation wireless receivers which are primarily designed to provide reasonable performance in terms of signal to noise ratio (SNR) and bit error rate (BER). However, none of them have been chosen for direct implementation as they offer high computational complexity with relatively lower computing power. This paper presents a low-complexity power-efficient algorithm that improves the computing power and provides relatively faster signal detection for next generation wireless multiuser receivers. Measurement results of the proposed algorithm are provided and the overall system performance is indicated by BER and the computational complexity. Finally, in order to verify the low-complexity of the proposed algorithm we also present a formal mathematical proof.

• Proceedings of the KSRS Conference
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• 2004.10a
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• pp.91-94
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• 2004

Ubiquitous sensor network is to manage and collect information autonomously by communicating user around device. Security requirements in Ubiquitous based on sensor network are as follows: a location of sensor, a restriction of performance by low electric power, communication by broadcasting, etc. We propose new mutual authentication protocol using a low power of sensor node. This protocol solved a low power problem by reducing calculation overload of sensor node using two steps, RM(Register Manager) and AM(Authentication Manager). Many operations performing the sensor node itself have a big overload in low power node. Our protocol reduces the operation number from sensor node. Also it is mutual authentication protocol in Ubiquitous network, which satisfies mutual authentication, session key establishment, user and device authentication, MITM attack, confidentiality, integrity, and is safe the security enemy with solving low electric power problem.

• Proceedings of the KIEE Conference
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• 2005.05a
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• pp.209-211
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• 2005

This paper proposes a adaptive medium-access control(MAC) protocol designed for low-power wireless multi-hop sensor networks which is used for connecting physical world and cyber computing space. Wireless multi-hop sensor networks use battery-operated computing and sensing device. We expect sensor networks to be deployed in an ad hoc fashion, with nodes remaining inactive for long time, but becoming suddenly active when specific event is detected. These characteristics of multi-hop sensor networks and applications motivate a MAC that is different from traditional wireless MACs about power conservation scheme, such as IEEE 802.11. Proposed MAC uses a few techniques to reduce energy consumption. Result show that proposed MAC obtains more energy savings.

• Journal of Semiconductor Engineering
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• v.2 no.3
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• pp.142-153
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• 2021

Recent research on synaptic devices has been reviewed from the perspective of hardware-based neuromorphic computing. In addition, the backgrounds of neuromorphic computing and two training methods for hardware-based neuromorphic computing are described in detail. Moreover, two types of memristor- and CMOS-based synaptic devices were compared in terms of both the required performance metrics and low-power applications. Based on a review of recent studies, additional power-scalable synaptic devices such as tunnel field-effect transistors are suggested for a plausible candidate for neuromorphic applications.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.769-772
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• 2005

This paper describes a low-voltage and low-power channel selection analog front end with continuous-time low pass filters and highly linear programmable-gain amplifier(PGA). The filters were realized as balanced Gm-C biquadratic filters to achieve a low current consumption. High linearity and a constant wide bandwidth are achieved by using a new transconductance(Gm) cell. The PGA has a voltage gain varying from 0 to 65dB, while maintaining a constant bandwidth. A filter tuning circuit that requires an accurate time base but no external components is presented. With a 1-Vrms differential input and output, the filter achieves -85dB THD and a 78dB signal-to-noise ratio. Both the filter and PGA were implemented in a 0.18um 1P6M n-well CMOS process. They consume 3.2mW from a 1.8V power supply and occupy an area of $0.19mm^2$.

• Journal of Information Processing Systems
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• v.17 no.3
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• pp.489-504
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• 2021

By distributing computing tasks among devices at the edge of networks, edge computing uses virtualization, distributed computing and parallel computing technologies to enable users dynamically obtain computing power, storage space and other services as needed. Applying edge computing architectures to Internet of Vehicles can effectively alleviate the contradiction among the large amount of computing, low delayed vehicle applications, and the limited and uneven resource distribution of vehicles. In this paper, a predictive offloading strategy based on the MEC load state is proposed, which not only considers reducing the delay of calculation results by the RSU multi-hop backhaul, but also reduces the queuing time of tasks at MEC servers. Firstly, the delay factor and the energy consumption factor are introduced according to the characteristics of tasks, and the cost of local execution and offloading to MEC servers for execution are defined. Then, from the perspective of vehicles, the delay preference factor and the energy consumption preference factor are introduced to define the cost of executing a computing task for another computing task. Furthermore, a mathematical optimization model for minimizing the power overhead is constructed with the constraints of time delay and power consumption. Additionally, the simulated annealing algorithm is utilized to solve the optimization model. The simulation results show that this strategy can effectively reduce the system power consumption by shortening the task execution delay. Finally, we can choose whether to offload computing tasks to MEC server for execution according to the size of two costs. This strategy not only meets the requirements of time delay and energy consumption, but also ensures the lowest cost.

• The Journal of the Korea institute of electronic communication sciences
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• v.18 no.2
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• pp.291-298
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• 2023

SRAM-based in-memory computing is one of the technologies to solve the bottleneck of von Neumann architecture. In order to achieve SRAM-based in-memory computing, it is essential to design efficient SRAM bit-cell. In this paper, we propose a low-power differential sensing 8+T SRAM bit-cell which reduces power consumption and improves circuit performance. The proposed 8+T SRAM bit-cell is applied to ripple carry adder which performs SRAM read and bitwise operations simultaneously and executes each logic operation in parallel. Compared to the previous work, the designed 8+T SRAM-based ripple carry adder is reduced power consumption by 11.53%, but increased propagation delay time by 6.36%. Also, this adder is reduced power-delay-product (PDP) by 5.90% and increased energy-delay- product (EDP) by 0.08%. The proposed circuit was designed using TSMC 65nm CMOS process, and its feasibility was verified through SPECTRE simulation.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.24 no.8
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• pp.985-992
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• 2020

Edge computing is a technology that can prepare for a new era of cloud computing. Edge computing is not a remote data center where data is processed and computed, but low-latency/high-speed computing is realized by adding computing power and data processing power to the edge side close to an access point such as a terminal device or a gateway. It is possible. The types of edge computing include mobile edge computing, fog computing, and cloudlet computing. In this article, we describes existing open source platforms for implementing edge computing nodes. By presenting and comparing the structure, features of open source edge platforms, it is possible to acquire knowledge required to select the best edge platform for industrial engineers who want to build an edge node using an actual open source edge computing platform.

• Journal of Communications and Networks
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• v.18 no.3
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• pp.327-332
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• 2016

The routing protocol for low-power and lossy networks (RPL) is an internet protocol based routing protocol developed and standardized by IETF in 2012 to support a wide range of applications for low-power and lossy-networks (LLNs). In LLNs consisting of resource-constrained devices, the energy consumption of battery powered sensing devices during network operations can greatly impact network lifetime. In the case of inefficient route selection, the energy depletion from even a few nodes in the network can damage network integrity and reliability by creating holes in the network. In this paper, a composite energy-aware node metric ($RER_{BDI}$) is proposed for RPL; this metric uses both the residual energy ratio (RER) of the nodes and their battery discharge index. This composite metric helps avoid overburdening power depleted network nodes during packet routing from the source towards the destination oriented directed acyclic graph root node. Additionally, an objective function is defined for RPL, which combines the node metric $RER_{BDI}$ and the expected transmission count (ETX) link quality metric; this helps to improve the overall network packet delivery ratio. The COOJA simulator is used to evaluate the performance of the proposed scheme. The simulations show encouraging results for the proposed scheme in terms of network lifetime, packet delivery ratio and energy consumption, when compared to the most popular schemes for RPL like ETX, hop-count and RER.

• JSTS:Journal of Semiconductor Technology and Science
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• v.11 no.3
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• pp.207-220
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• 2011

Coarse-grained reconfigurable architecture (CGRA) based embedded systems aims to achieve high system performance with sufficient flexibility to map a variety of applications. However, the CGRA has been considered as prohibitive one due to its significant area/power overhead and performance bottleneck. In this work, I propose reconfigurable multi-array architecture to reduce power/area and enhance performance in configurable embedded systems. The CGRA-based embedded systems that consist of hierarchical configurable computing arrays with varying size and communication speed were examined for multimedia and other applications. Experimental results show that the proposed approach reduces on-chip area by 22%, execution time by up to 72% and reduces power consumption by up to 55% when compared with the conventional CGRA-based architectures.