• 전기학회논문지P
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• 제61권3호
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• pp.149-152
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• 2012

In this paper, a wideband monopole antenna with ring loop by modified ground plane is presented. The proposed antenna consist of monopole antenna, ring loop by ground plane. This antenna is fed CPW-fed and wide slot antenna of a novel structure for broadband characteristics is proposed. To enhance the impedance bandwidth of the wide slot antenna, we proposed the wide slot structure with CPW-fed which is combined with four ${\lambda}/2$ rectangular radiation modified monopole and inductively coupled. The measured impedance bandwidth is about 2.5 GHz(3.65~6.15 GHz) then less -10 dB.

• 대한전기학회논문지:시스템및제어부문D
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• 제49권5호
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• pp.278-286
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• 2000

A new large-scale network geometric analysis is introduced. For a large-scale circuit, it must be analyzed with a geometric diagram and figure. So many equations are induced from a geometric loop-node diagram. The results are arranged into a simple matrix, of course. In case of constructing a network diagram, it is not easy to handle voltage and current sources together. Geometric loop analysis is related to voltage sources, and node analysis is to current sources. The reciprocal transfer is possible only to have series or parallel impedance. If not having this impedance, in order to obtain equivalent circuit, many equations must be derived. In this paper a loop-reduction method is proposed. With this method current source branch is included into the other branch, and disappears in circuit diagram. So the number of independent circuit equations are reduced as much as that of current sources. The number is not (b-n+1), but (b-n+1-p). Where p is the number of current sources. The reduction procedure is verified with a geometric principle and circuit theory. A resultant matrix can be constructed directly from this diagram structure, not deriving circuit equations. We will obtain the last results with the help of a computer.

• 한국정보통신학회:학술대회논문집
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• 한국정보통신학회 2017년도 추계학술대회
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• pp.55-56
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• 2017

본 논문에서는 동일면 도파관(CPW; coplanar waveguide) 급전 방식을 이용하여 실내 디지털 TV(DTV)용 광대역 루프 안테나를 설계하였다. 제안된 루프 안테나는 정사각형 루프와 중앙 급전점을 연결하는 두 개의 원형 섹터로 구성되며, 아래쪽 원형섹터에 CPW 급전선로가 삽입된 형태이다. CPW 급전선로는 DTV응용을 위해 75옴 포트 임피던스와 정합하도록 설계되었으며, 중간 주파수 대역에서 임피던스 정합을 개선하기 위한 슬롯이 접지면에 추가되었다. 최적화된 안테나를 FR4 기판에 제작하고 특성을 실험한 결과, 전압 정재파비(VSWR; voltage standing wave) < 2인 대역이 463-1,280 MHz으로 DTV 대역에서 동작하는 것을 확인하였다.

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2003년도 춘계학술대회 논문집
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• pp.325-329
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• 2003

In this paper. the stability and performance analysis of wave-based teleoperation system is presented. For stability and performance analysis with respect to the variation of characteristic impedance b, loop gains of communication channel and minimum value of trasmitted impedance from slave side to the master side are considered. The stability of slave side may be enhanced by increasing characteristic impedance b, whereas exssively high value of b may degrade the performance, which imply a tradeoff between stability and performance.

• 조명전기설비학회논문지
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• 제23권5호
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• pp.36-41
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• 2009

본 논문에서는 건축물 전기설비의 IEC 60364를 기반으로 개발된 점검기법을 이용하여 실태 조사를 실시하였다. 점검기법 개발을 위한 분석대상은 기술기준에 준하여 시공된 국내 건축전기설비와 IEC 60364로 시공된 건축전기설비를 대상으로 차이점을 분석하였다. 측정 요소는 Loop impedance, 차단기 동작특성, 보호도체의 연속성을 측정하였다. 조사결과 국내 건축전기설비의 경우 TT시스템과 유사하지만 보호도체의 연속성에 문제가 있었다. TN-C-S로 시공된 건축전기설비의 경우 시공은 정확하게 되어 있었으나 담당자의 IEC 60364와 관련된 이해가 부족한 상태였다.

• Journal of Electrical Engineering and Technology
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• 제6권4호
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• pp.551-555
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• 2011

The Crab label tag with a loop matching feed and a modified dipole antenna structure was proposed. The antenna impedance is conjugated easily to a radio frequency identification IC chip impedance by a loop matching feed. The reading range of the crab structure tag is 0.9-1.0 m from the upper side of the formula milk can lid. The fabricated label tag size is $44.0{\times}44.0mm^2$. The operating frequency at -3 dB return loss is 861.0-929.0 MHz, and the maximum reading range at the anechoic chamber is 1.5 m.

• Journal of information and communication convergence engineering
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• 제10권2호
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• pp.103-107
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• 2012

An end-launched adapter combining a coaxial loop within a rectangular waveguide has been analyzed and designed. The accurate electromagnetic modeling of input impedance for the adapter design has been developed using a modal analysis method. Also, design parameters to improve the end-launched adapter have been investigated. Numerical and experimental results of the proposed model have been compared with the results of previous works, and verified by an electromagnetic simulator of High Frequency Structure Simulator (HFSS). The input voltage standing wave ratios (VSWRs) are smaller than 2 over the wide frequency band from 7.5 GHz to 10.5 GHz.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 하계종합학술대회 논문집(5)
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• pp.39-42
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• 2000

In this paper we design the robust impedance controller of the robot manipulator with time delay. The designed controller considers time delay in the position loop and stabilizes the closed-loop system. The performance of a controller can be easily degraded by external disturbances. To improve the performance when external disturbances exist, we use the disturbance observer to handle the disturbances in the velocity loop and provide robustness to the control system. To show the validity of the designed controller, several experiments are performed for the 5-DOF robot manipulator equipped with the wrist force/torque sensor system.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 ITC-CSCC -2
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• pp.604-607
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• 2000

In this paper we design the robust impedance controller of the robot manipulator with time delay. The designed controller considers time delay in the position loop and stabilizes the closed-loop system. The performance of a controller can be easily degraded by external disturbances. To improve the performance when external disturbances exist, we use the disturbance observer to handle the disturbances in the velocity loop and provide robustness to the control system. To show the validity of the designed controller, several experiments are performed for the 5-DOF robot manipulator equipped with the wrist force/torque sensor system.

• 대한전자공학회논문지SD
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• 제45권4호
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• pp.146-153
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• 2008

High speed serial link에 적합한 clock multiphase generator용 integrated phase-locked loop (PLL)을 설계하였다. 설계된 PLL은 programmable current mirror를 사용하여 동작 범위 안에서 동일한 loop bandwidth와 damping factor를 가진다. 또한 설계한 PLL 회로 netlists를 가지고 HSPICE 시뮬레이션을 통해 close-loop transfer function과 VCO의 phase noise transfer function을 구하였다. Board 위 칩의 자체 임피던스는 decoupling capacitor의 크기와 위치에 따라 계산된다. 세부적으로, close-loop transfer function에서 gain의 최대값과 VCO noise transfer function에서 gain의 최대값 사이의 주파수범위에서 decoupling capacitor의 크기와 위치에 따른 보드 위 칩의 자체 임피던스를 구하였다. 이를 바탕으로 보드에서의 decoupling capacitor의 크기와 위치가 PLL의 jitter에 어떠한 영향을 미치는지 분석하였다. 설계된 PLL은 1.8V의 동작 전압에서 400MHz에서 2GH의 wide operation range를 가지며 $0.18-{\mu}m$ EMOS공정으로 설계하였다. Reference clock은 100MHz이며 전체 PLL power consumption은 1.2GHz에서 17.28 mW이다.