• Management Science and Financial Engineering
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• v.12 no.2
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• pp.37-62
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• 2006

This paper considers the problem of designing logical tunnels in virtual private networks considering QoS guarantee which restricts the number of tunnel hops for each traffic routing. The previous researches focused on the design of logical tunnel itself and Steiner-tree based solution algorithms were proposed. However, we show that for some objective settings it is not sufficient and is necessary to consider both physical and logical connectivity at the same time. Thereupon, the concept of the layered network is applied to the logical tunnel design problem in virtual private networks. The layered network approach considers the design of logical tunnel as well as its physical routing and we propose a modified branch-and-price algorithm which is known to solve layered network design problems effectively. To show the performance of the proposed algorithm, computational experiments have been done and the results show that the proposed algorithm solves the given problem efficiently and effectively.

• Journal of Korean Institute of Industrial Engineers
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• v.37 no.3
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• pp.264-270
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• 2011

A new method for creating a logical data model is proposed. The logical data model developed by the method defines table, primary key, foreign key, and fields. The framework of the logical data model is constructed by modeling the relationships between events and their related entity types. The proposed method consists of a series of objective and quantitative decisions such as maximum cardinality of relationships and functional dependency between the primary key and attributes. Even beginners to database design can use the methology as long as they understand such basic concepts about relational databases as primary key, foreign key, relationship cardinality, parent-child relationship, and functional dependency. The simple and systematic approach minimizes decision errors made by a database designer. In practial database design the method creates a logical data model in Boyce-Codd normal form unless the user of the method makes a critical decision error, which is very unlikely.

• Journal of the Semiconductor & Display Technology
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• v.2 no.4
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• pp.1-7
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• 2003

In this paper, we design the pattern generator circuits using PLDs(Programmable Logic Devices). The pattern generator is the circuit which generates the test pattern signal for the inspection of logical defects of semiconductor products. The proposed circuits are designed by the PLD design tool(MAX+ II of ALTERA). Also the designed circuits are simulated for the verification of the designed ones. The simulation results have a good performance.

• The KIPS Transactions:PartA
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• v.17A no.1
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• pp.27-32
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• 2010

Logical Effort is a simple hand-calculated method that measures quick delay estimation. It has the advantage of reducing the design cycle time. However, it has shortcomings in designing a path for minimum area or power under a fixed-delay constraint. In this paper, we propose an equal delay model and, based on this, a method of optimizing power-delay efficiency in a logical path. We simulate three designs of an eight-input AND gate using our technique. Our results show about 40% greater efficiency in power dissipation than those of Logical Effort method.

• Korean Journal of Computational Design and Engineering
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• v.14 no.4
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• pp.225-233
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• 2009

The objective of this paper is to examine a construction method and verify PLC logic using the logical modeling and simulation of a virtual plant has complex manufacturing system and the domain of application is car body assembly line of automotive industrial operated by PLC Program. The proposed virtual plant model for the analysis of the construction method consists of three types of components which are virtual device, intermediary transfer and controller is modeled by logical model but it the case of the verification of PLC program, HMI and PLC logic in the field substitute for the controller. The implementation of the proposed virtual plant model is conducted PLC Studio which is an object-oriented modeling language based on logical model. As a result, proposed methods enable 3D graphics is designed in the analysis step to use for verification of PLC program without special efforts.

• Journal of the Optical Society of Korea
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• v.19 no.1
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• pp.13-21
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• 2015

In recent years energy consumption has become a main concern for network development, due to the exponential increase of network traffic. Potential energy savings can be obtained from a load-adaptive scheme, in which a day can be divided into multiple time periods according to the variation of daily traffic patterns. The energy consumption of the network can be reduced by selectively turning off network components during the time periods with light traffic. However, the time segmentation of daily traffic patterns affects the energy savings when designing multiperiod logical topology in optical wavelength routed networks. In addition, turning network components on or off may increase the overhead of logical topology reconfiguration (LTR). In this paper, we propose two mixed integer linear programming (MILP) models to design the optimal logical topology for multiple periods in IP-over-WDM networks. First, we formulate the time-segmentation problem as an MILP model to optimally determine the boundaries for each period, with the objective to minimize total network energy consumption. Second, another MILP formulation is proposed to minimize both the overall power consumption (PC) and the reconfiguration overhead (RO). The proposed models are evaluated and compared to conventional schemes, in view of PC and RO, through case studies.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.61 no.3
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• pp.491-496
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• 2012

There are several protective relays used to protect DC traction power supply system for DC railway. These relays, however, are made by different manufactures and they have different ways for their operations. Therefore, there are difficulties for cooperation between the devices or the devices and an upper system. In order to increase interoperability and stability of the system composed of devices made by different manufactures, IEC 61850 international standards are applied to design logical nodes for modeling protective elements used in protective relays.

• Proceedings of the KSR Conference
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• 2008.11b
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• pp.465-474
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• 2008

This research presented an extraction method of a logical database to create a design form of stream-nose. The practical use of logical database is important for the expansion of thinking area with investigation of Form to create a stream nose. Firstly, We presented apply course with the method to draw the image database as a first step of a stream-nose design. secondly, extraction method of a character-line applied the image-layered technique was an objectified. Such course is for establishing a design process to create the original form of the stream nose.

• Proceedings of the Computational Structural Engineering Institute Conference
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• 2004.10a
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• pp.126-132
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• 2004

The database design for the management of bridge measurement information is presented in this paper. To express the associated data generated during the whole process of ambient measurement efficiently, requirements analysis for database construction is performed. And to define objects and organize schema conceptual and logical design are performed, which convert data model into logical schema. Finally, physical design is performed using DDL(data defined language). This database is based on the object-relational data modeling approach that has rich expressive power and good reusability in comparison with the traditional entity-relational modeling.

• ETRI Journal
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• v.33 no.5
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• pp.695-703
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• 2011

The number of adders and critical paths in a multiplier block of a multiple constant multiplication based implementation of a finite impulse response (FIR) filter can be minimized through common subexpression elimination (CSE) techniques. A two-bit common subexpression (CS) can be located recursively in a noncanonic sign digit (CSD) representation of the filter coefficients. An efficient algorithm is presented in this paper to improve the elimination of a CS from the multiplier block of an FIR filter so that it can be realized with fewer adders and low logical depth as compared to the existing CSE methods in the literature. Vinod and others claimed the highest reduction in the number of logical operators (LOs) without increasing the logic depth (LD) requirement. Using the design examples given by Vinod and others, we compare the average reduction in LOs and LDs achieved by our algorithm. Our algorithm shows average LO improvements of 30.8%, 5.5%, and 22.5% with a comparative LD requirement over that of Vinod and others for three design examples. Improvement increases as the filter order increases, and for the highest filter order and lowest coefficient width, the LO improvements are 70.3%, 75.3%, and 72.2% for the three design examples.