• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 2005년도 ISMP
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• pp.111-129
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• 2005

Pop provides OEMs and EMS with a platform to cost effectively expand options for logic + memory 3D integration - Expands device options by simplifying business logistics of stacking - Integration controlled at the system level to best match stacked combinations with system requirements - Eliminates margin stacking and expands technology reuse - Helps manage the huge cost impacts associated with increasing demand for multi media processing and memory. PoP is well timed to enable and leverage: - Mass customization of systems for different use (form, fit and function) requirements o Bband and apps processor + memory stack platforms - Logic transition to flip chip enables PoP size reduction o Area and height reduction. Industry standardization is progressing. Amkor provides full turn-key support for base package, memory package and full system integration.

• 센서학회지
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• 제26권3호
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• pp.209-213
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• 2017

The delay-insensitive Null Convention Logic (NCL) asynchronous design as one of innovative asynchronous logic design methodologies has many advantages of inherent robustness, power consumption, and easy design reuses. However, transistor-level structures of conventional NCL gate cells have weakness of high area overhead and high power consumption. This paper proposes a new NCL gate based on power gating structure. The proposed $4{\times}4$ NCL multiplier based on power gating structure is compared to the conventional NCL $4{\times}4$ multiplier and MTNCL(Multi-Threshold NCL) $4{\times}4$ multiplier in terms of speed, power consumption, energy and size using PTM 45 nm technology.

• Journal of Electrical Engineering and Technology
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• 제5권3호
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• pp.415-422
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• 2010

The distributed flexible alternative current transmission system (D-FACTS) is a recently developed FACTS technology. Distributed Static Series Compensator (DSSC) is one example of DFACTS devices. DSSC functions in the same way as a Static Synchronous Series Compensator (SSSC), but is smaller in size, lower in price, and possesses more capabilities. Likewise, DSSC lies in transmission lines in a distributed manner. In this work, we designed a fuzzy logic controller to use the DSSC for enhancing transient stability in a two-machine, two-area power system. The parameters of the fuzzy logic controller are varied widely by a suitable choice of membership function and parameters in the rule base. Simulation results demonstrate the effectiveness of the fuzzy controller for transient stability enhancement by DSSC.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 ITC-CSCC -1
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• pp.179-182
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• 2000

Adiabatic dynamic CMOS logic circuits, which are called ADCL circuits, promise us to implement low power logic circuits. Since the power supply source for ADCL circuits had not been developed, we proposed a power supply circuit for them. It is shown experimentally that by using the power supply circuit ADCL circuits can work with lower power consumption than conventional static CMOS circuit. In this paper, the power supply circuit is improved so that the power consumption can be reduced. Also, it is shown by some experiments that by using the circuit, ADCL circuits can work with lower power consumption than before Improving.

• 대한전자공학회논문지
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• 제22권6호
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• pp.13-18
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• 1985

고밀도 PLA(Programmable Logic Array) layout의 생성, 간소화 및 검증을 자동화한 일련의 유용프로그램을 개발하였다. 이에는 논리 함수로부터 진리표를 만들어 내는 프로그램. 논리 간소화 프로그램 PLA재배열 프로그랭. stick diagram을 그릴 구 있는 화일을 만들어 내는 프로그램, dynamic CMOS PLA의 layout 생성 프로그램, 그리고 bipartite row folded CMOS PLA layout 생성 프로그램이 포함된다. 크기의 최소화는 주로 논리 간소화 프로그램과 bipartlte row folding 프로그램에 의해수행되며, 최대지연시간은 재배열 프로그램에 의해 작아진다. 자동으로 생성된 layout에 대한 정보는 CIF(Caltach Int-ermidate Form)로 저장된다. 각 프로그램은 C언어로 작성되었으며, VAX-l1/750 (UNIX)에서 수행되었다.

• Journal of Electrical Engineering and Technology
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• 제4권1호
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• pp.66-78
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• 2009

This paper introduces the design of a fuzzy logic controller in conjunction with direct torque control strategy for a Permanent Magnet synchronous machine. A stator flux angle mapping technique is proposed to reduce significantly the size of the rule base to a great extent so that the fuzzy reasoning speed increases. Also, a fuzzy resistance estimator is developed to estimate the change in the stator resistance. The change in the steady state value of stator current for a constant torque and flux reference is used to change the value of stator resistance used by the controller to match the machine resistance.

• International Journal of Computer Science & Network Security
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• 제24권6호
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• pp.17-22
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• 2024

Software cost and schedule estimation is usually based on the estimated size of the software. Advanced estimation techniques also make use of the diverse factors viz, nature of the project, staff skills available, time constraints, performance constraints, technology required and so on. Usually, estimation is based on an estimation model prepared with the help of experienced project managers. Estimation of software cost is predominantly a crucial activity as it incurs huge economic and strategic investment. However accurate estimation still remains a challenge as the algorithmic models used for Software Project planning and Estimation doesn't address the true dynamic nature of Software Development. This paper presents an efficient approach using the contemporary Constructive Cost Model (COCOMO) augmented with the desirable feature of fuzzy logic to address the uncertainty and flexibility associated with the cost drivers (Effort Multiplier Factor). The approach has been validated and interpreted by project experts and shows convincing results as compared to simple algorithmic models.

• 대한전자공학회논문지SD
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• 제44권10호
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• pp.33-37
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• 2007

본 논문에서는 vertical shunt symmetric inductor를 이용하여 CMOS LNA의 설계에 있어서 회로의 면적을 줄이는 설계기술 및 구현에 관한 내용을 제시하고자 한다. 본 연구에 있어서 vertical shunt symmetric inductor는 LNA의 입력단과 출력단을 3GHz로 정합하기 위해서 사용되었다. 이렇게 구현된 보다 면적에 있어서 효율적인 증폭기를 0.18um digital logic공정으로 구현되었다. 본 논문에서는 일반적으로 LNA에서 사용하고 있는 inductor를 이용하는 경우와, vertical shunt symmetric inductor를 이용하여 LNA를 설계하는 경우에 대한 부분을 비교하였고, 최종적으로 면적에 효율적인 회로설계 기술을 제시하고자 한다.

• Advances in materials Research
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• 제1권2호
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• pp.129-146
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• 2012

Polycrystalline diamond is an ideal material for parts with micro-holes and has been widely used as dies and cutting tools in automotive, aerospace and woodworking industries due to its superior wear and corrosion resistance. In this research paper, the modeling and simultaneous optimization of multiple performance characteristics such as material removal rate and surface roughness of polycrystalline diamond (PCD) with ultrasonic machining process has been presented. The fuzzy logic and taguchi's quality loss function has been used. In recent years, fuzzy logic has been used in manufacturing engineering for modeling and monitoring. Also the effect of controllable machining parameters like type of abrasive slurry, their size and concentration, nature of tool material and the power rating of the machine has been determined by applying the single objective and multi-objective optimization techniques. The analysis of results has been done using the MATLAB 7.5 software and results obtained are validated by conducting the confirmation experiments. The results show the considerable improvement in S/N ratio as compared to initial cutting conditions. The surface roughness of machined surface has been measured by using the Perthometer (M4Pi, Mahr Germany).

• 전자공학회논문지
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• 제51권4호
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• pp.42-48
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• 2014

본 논문에서는, 트위스티드 연결구조를 이용한 새로운 저전압 스윙 도미노 로직 회로를 제안한다. 제안된 회로의 출력스윙 범위는 트위스티드 트랜지스터의 사이즈와 출력 캐패시턴스의 크기에 따라 조절가능하다. 제안된 회로를 적용한 리플캐리덧셈기(Ripple Carry Adder)는 도미노 CMOS로직에 비해 전력소비는 37%감소했고 전력 지연 곱(power-delay product)은 43%감소했다.