• Title/Summary/Keyword: Logic size

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A Parallel Hardware Architecture for H.264/AVC Deblocking Filter (H.264/AVC를 위한 블록현상 제거필터의 병렬 하드웨어 구조)

  • Jeong, Yong-Jin;Kim, Hyun-Jip
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.43 no.10 s.352
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    • pp.45-53
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    • 2006
  • In this paper, we proposed a parallel hardware architecture for deblocking filter in K264/AVC. The deblocking filter has high efficiency in H.264/AVC, but it also has high computational complexity. For real time video processing, we chose a two 1-D parallel filter architecture, and tried to reduce memory access using dual-port SRAM. The proposed architecture has been described in Verilog-HDL and synthesized on Hynix 0.25um CMOS Cell Library using Synopsys Design Compiler. The hardware size was about 27.3K logic gates (without On-chip Memory) and the maximum operating frequency was 100Mhz. It consumes 258 clocks to process one macroblock, witch means it can process 47.8 HD1080P(1920pixel* 1080pixel) frames per second. It seems that it can be used for real time H.264/AVC encoding and decoding of various multimedia applications.

A 2.5Gb/s 2:1 Multiplexer Design Using Inductive Peaking in $0.18{\mu}m$ CMOS Technology (Micro spiral inductor를 이용한 2.5Gb/s급 2:1 Multiplexer 설계)

  • Kim, Sun-Jung;Choi, Jung-Myung;Burm, Jin-Wook
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.44 no.8
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    • pp.22-29
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    • 2007
  • A 2.5Gb/s 2:1 multiplexer(MUX) IC using $0.18{\mu}m$ CMOS was designed and fabricated. Inductive peaking technology was used to improve the performance. On-chip micro spiral inductor was designed to maximize the inductive peaking effect without increasing the chip area much. The designed 4.7 nH micro-spiral inductor was $20\times20{\mu}m2$ in size. 2:1 MUX with and without micro spiral inductors were compared. The rise and fall time was improved more than 23% and 3% respectively using the micro spiral inductors for 1.25Gb/s signal. For 2.5 Gb/s signal, fall and rise time was improved 5.3% and 3.5% respectively. It consumed 61mW and voltage output swing was 1$180mV_{p-p}$ at 2.5Gb/s.

A Low-Complexity Real-Time Barrel Distortion Correction Processor Combined with Color Demosaicking (컬러 디모자이킹이 결합된 저 복잡도의 실시간 배럴 왜곡 보정 프로세서)

  • Jeong, Hui-Seong;Park, Yun-Ju;Kim, Tae-Hwan
    • Journal of the Institute of Electronics and Information Engineers
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    • v.51 no.9
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    • pp.57-66
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    • 2014
  • This paper presents a low-complexity barrel distortion correction processor for wide-angle cameras. The proposed processor performs the barrel distortion correction jointly with the color demosaicking, so that the hardware complexity can be reduced significantly. In addition, to reduce the required memory bandwidth, an efficient memory interface is proposed by utilizing the spatial locality of the memory access in the correction process. The proposed processor is implemented with 35K logic gates in a $0.11-{\mu}m$ CMOS process and its correction speed is 150 Mpixels/s at the operating frequency of 606MHz, where the supported frame size is $2048{\times}2048$ and the required memory bandwidth is 1 read/cycle.

3-D Hetero-Integration Technologies for Multifunctional Convergence Systems

  • Lee, Kang-Wook
    • Journal of the Microelectronics and Packaging Society
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    • v.22 no.2
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    • pp.11-19
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    • 2015
  • Since CMOS device scaling has stalled, three-dimensional (3-D) integration allows extending Moore's law to ever high density, higher functionality, higher performance, and more diversed materials and devices to be integrated with lower cost. 3-D integration has many benefits such as increased multi-functionality, increased performance, increased data bandwidth, reduced power, small form factor, reduced packaging volume, because it vertically stacks multiple materials, technologies, and functional components such as processor, memory, sensors, logic, analog, and power ICs into one stacked chip. Anticipated applications start with memory, handheld devices, and high-performance computers and especially extend to multifunctional convengence systems such as cloud networking for internet of things, exascale computing for big data server, electrical vehicle system for future automotive, radioactivity safety system, energy harvesting system and, wireless implantable medical system by flexible heterogeneous integrations involving CMOS, MEMS, sensors and photonic circuits. However, heterogeneous integration of different functional devices has many technical challenges owing to various types of size, thickness, and substrate of different functional devices, because they were fabricated by different technologies. This paper describes new 3-D heterogeneous integration technologies of chip self-assembling stacking and 3-D heterogeneous opto-electronics integration, backside TSV fabrication developed by Tohoku University for multifunctional convergence systems. The paper introduce a high speed sensing, highly parallel processing image sensor system comprising a 3-D stacked image sensor with extremely fast signal sensing and processing speed and a 3-D stacked microprocessor with a self-test and self-repair function for autonomous driving assist fabricated by 3-D heterogeneous integration technologies.

Enhanced Processor-Architecture for the Faster Processing of Genetic Algorithm (유전 알고리즘 처리속도 향상을 위한 강화 프로세서 구조)

  • Yoon, Han-Ul;Sim, Kwee-Bo
    • Journal of the Korean Institute of Intelligent Systems
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    • v.15 no.2
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    • pp.224-229
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    • 2005
  • Generally, genetic algorithm (GA) has too much time and space complexity when it is running in the typical processor. Therefore, we are forced to use the high-performance and expensive processor by this reason. It also works as a barrier to implement real device, such a small mobile robot, which is required only simple rules. To solve this problem, this paper presents and proposes enhanced processor-architecture for the faster GA processing. A typical processor architecture can be enhanced and specialized by two approaches: one is a sorting network, the other is a residue number system (RNS). A sorting network can improve the time complexity of which needs to compare the populations' fitness. An RNS can reduce the magnitude of the largest bit that dictates the speed of arithmetic operation. Consequently, it can make the total logic size smaller and innovate arithmetic operation speed faster.

An Optimal Design of a TDMA Baseband Modem for Relay Protocol (중계 프로토콜을 위한 TDMA 기저대역 중계모뎀의 최적 설계)

  • Bae, Yongwook;Ahn, Byoungchul
    • Journal of the Institute of Electronics and Information Engineers
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    • v.51 no.6
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    • pp.124-131
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    • 2014
  • This paper describes a design of an adaptive baseband modem based on TDMA(time division multiple access) with a relay protocol function for wireless personal area networks. The designed baseband modem is controlled by a master synchronization signal and can be configured a relay network up to 14 hops. For efficient data relay communications, the internal buffer design is optimized by implementing a priority memory bus controller to a single port memory. And the priority memory bus controller is also designed to minimize the number of synthesized logic gates. To implement the synchronization function of the narrowband TDMA relay communication, the number of gates has been reduced by dividing the frame synchronization circuits and the network slot synchronization circuits. By using these methods, the number of gates are used about 37%(34,000 gates) on Xilinx FPGA XC6SLX9 which has 90,000 gates. For the 1024-bit frame size with a 32-bit synchronization word, the communication reception rate is 96.4%. The measured maximum transmission delay of the designed baseband modem is 230.4 msec for the 14-hop relay communication.

PC-based Hand-Geometry Verification System

  • Kim Young-Tak;Kim Soo-Jong;Lee Chang-Gyu;Kim Gwan-Hyung;Kang Sung-In;Lee Jae-Hyun;Tack Han-Ho;Lee Sang-Bae
    • International Journal of Fuzzy Logic and Intelligent Systems
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    • v.6 no.3
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    • pp.247-254
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    • 2006
  • Biometrics are getting more and more attention in recent years for security and other concerns. So far, only fingerprint recognition has seen limited success for on-line security check, since other biometrics verification and identification systems require more complicated and expensive acquisition interfaces and recognition processes. Hand-Geometry can be used for biometric verification and identification because of its acquisition convenience and good performance for verification and identification performance. It could also be a good candidate for online checks. Therefore, this paper proposes a Hand-Geometry recognition system based on geometrical features of hand. From anatomical point of view, human hand can be characterized by its length, width, thickness, geometrical composition, shapes of the palm, and shape and geometry of the fingers. This paper proposes thirty relevant features for a Hand-Geometry recognition system. This system presents verification results based on hand measurements of 20 individuals. The verification process has been tested on a size of $320{\times}240$ image, and result of the verification process have hit rate of 95% and FAR of 0.020.

A Design of Interger division instruction of Low Power ARM7 TDMI Microprocessor (저전력 ARM7 TDMI의 정수 나눗셈 명령어 설계)

  • 오민석;김재우;김영훈;남기훈;이광엽
    • Journal of the Institute of Electronics Engineers of Korea CI
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    • v.41 no.4
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    • pp.31-39
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    • 2004
  • The ARM7 TDMI microprocessor employ a software routine iteration method in order to handle integer division operation, but this method has long execution time and many execution instruction. In this paper, we proposed ARM7 TDMI microprocessor with integer division instruction. To make this, we additionally defined UDIV instruction for unsigned integer division operation and SDIV instruction for signed integer division operation, and proposed ARM7 TDMI microprocessor data Path to apply division algorithm. Applied division algorithm is nonrestoring division algorithm and additive hardware is reduced using existent ARM data path. To verify the proposed method, we designed proposed method on RTL level using HDL, and conducted logic simulation. we estimated the number of execution cycles and the number of execution instructions as compared proposed method with a software routine iteration method, and compared with other published integer divider from the number of execution cycles and hardware size.

Design of efficient self-repair system for multi-faults (다중고장에 대한 효율적인 자가치유시스템 설계)

  • Choi, Ho-Yong;Seo, Jung-Il;Yu, Chung-Ho;Woo, Cheol-Jong;Lee, Jae-Eun
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.43 no.11 s.353
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    • pp.69-76
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    • 2006
  • This paper proposes a self-repair system which is able to self-repair in cell unit by imitating the structure of living beings. Because the data of artificial cells move even diagonally, our system can self-repair faults not in column unit, but in cell unit. It leads to design an efficient self-repair system for multiple faults. Moreover, in artificial cell design, the usage of logic-based design method has smaller system size than that of the previous register-based design method. Our experimental result for 2-bit up/down counter shows 40.3% reduction in hardware overhead, compared to the previous method [6].

Hardware design of Reed-solomon decoder for DMB mobile terminals (DMB 휴대용 단말기를 위한 Reed-Solomon 복호기의 설계)

  • Ryu Tae-Gyu;Jeong Yong-Jin
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.43 no.4 s.346
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    • pp.38-48
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    • 2006
  • In this paper, we developed a hardware architecture of Reed-Solomon RS(255,239) decoder for the DMB mobile terminals. The DMB provides multimedia broadcasting service to mobile terminals, hence it should have small dimension for low power and short decoding delay for real-time processing. We modified Euclid algorithm to apply it to the key equation solving which is the most complicated part of the RS decoding. We also designed a small finite field divider to avoid the use of large Inverse-ROM table, and it consumed 17 clocks. After synthesis with Synopsis on Samsung STD130 $0.18{\mu}m$ Standard Cell library, the Euclid block had 30,228 gates and consumed 288 clocks, which gave the 25% reduced area compared to other existing designs. The size of the entire RS decoder was about 45,000 gates.