• Title/Summary/Keyword: Logic size

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The Linear Discrepancy of a Fuzzy Poset

  • Cheong, Min-Seok;Chae, Gab-Byung;Kim, Sang-Mok
    • International Journal of Fuzzy Logic and Intelligent Systems
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    • v.11 no.1
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    • pp.59-64
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    • 2011
  • In 2001, the notion of a fuzzy poset defined on a set X via a triplet (L, G, I) of functions with domain X ${\times}$ X and range [0, 1] satisfying a special condition L+G+I = 1 is introduced by J. Negger and Hee Sik Kim, where L is the 'less than' function, G is the 'greater than' function, and I is the 'incomparable to' function. Using this approach, we are able to define a special class of fuzzy posets, and define the 'skeleton' of a fuzzy poset in view of major relation. In this sense, we define the linear discrepancy of a fuzzy poset of size n as the minimum value of all maximum of I(x, y)${\mid}$f(x)-f(y)${\mid}$ for f ${\in}$ F and x, y ${\in}$ X with I(x, y) > $\frac{1}{2}$, where F is the set of all injective order-preserving maps from the fuzzy poset to the set of positive integers. We first show that the definition is well-defined. Then, it is shown that the optimality appears at the same injective order-preserving maps in both cases of a fuzzy poset and its skeleton if the linear discrepancy of a skeleton of a fuzzy poset is 1.

An Efficient 5-Input Exclusive-OR Circuit Based on Carbon Nanotube FETs

  • Zarhoun, Ronak;Moaiyeri, Mohammad Hossein;Farahani, Samira Shirinabadi;Navi, Keivan
    • ETRI Journal
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    • v.36 no.1
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    • pp.89-98
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    • 2014
  • The integration of digital circuits has a tight relation with the scaling down of silicon technology. The continuous scaling down of the feature size of CMOS devices enters the nanoscale, which results in such destructive effects as short channel effects. Consequently, efforts to replace silicon technology with efficient substitutes have been made. The carbon nanotube field-effect transistor (CNTFET) is one of the most promising replacements for this purpose because of its essential characteristics. Various digital CNTFET-based circuits, such as standard logic cells, have been designed and the results demonstrate improvements in the delay and energy consumption of these circuits. In this paper, a new CNTFET-based 5-input XOR gate based on a novel design method is proposed and simulated using the HSPICE tool based on the compact SPICE model for the CNTFET at the 32-nm technology node. The proposed method leads to improvements in performance and device count compared to the conventional CMOS-style design.

A Suggestion for Data Assimilation Method of Hydrometeor Types Estimated from the Polarimetric Radar Observation

  • Yamaguchi, Kosei;Nakakita, Eiichi;Sumida, Yasuhiko
    • Proceedings of the Korea Water Resources Association Conference
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    • 2009.05a
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    • pp.2161-2166
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    • 2009
  • It is important for 0-6 hour nowcasting to provide for a high-quality initial condition in a meso-scale atmospheric model by a data assimilation of several observation data. The polarimetric radar data is expected to be assimilated into the forecast model, because the radar has a possibility of measurements of the types, the shapes, and the size distributions of hydrometeors. In this paper, an impact on rainfall prediction of the data assimilation of hydrometeor types (i.e. raindrop, graupel, snowflake, etc.) is evaluated. The observed information of hydrometeor types is estimated using the fuzzy logic algorism. As an implementation, the cloud-resolving nonhydrostatic atmospheric model, CReSS, which has detail microphysical processes, is employed as a forecast model. The local ensemble transform Kalman filter, LETKF, is used as a data assimilation method, which uses an ensemble of short-term forecasts to estimate the flowdependent background error covariance required in data assimilation. A heavy rainfall event occurred in Okinawa in 2008 is chosen as an application. As a result, the rainfall prediction accuracy in the assimilation case of both hydrometeor types and the Doppler velocity and the radar echo is improved by a comparison of the no assimilation case. The effects on rainfall prediction of the assimilation of hydrometeor types appear in longer prediction lead time compared with the effects of the assimilation of radar echo only.

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A neural network approach to defect classification on printed circuit boards (인쇄 회로 기판의 결함 검출 및 인식 알고리즘)

  • An, Sang-Seop;No, Byeong-Ok;Yu, Yeong-Gi;Jo, Hyeong-Seok
    • Journal of Institute of Control, Robotics and Systems
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    • v.2 no.4
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    • pp.337-343
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    • 1996
  • In this paper, we investigate the defect detection by making use of pre-made reference image data and classify the defects by using the artificial neural network. The approach is composed of three main parts. The first step consists of a proper generation of two reference image data by using a low level morphological technique. The second step proceeds by performing three times logical bit operations between two ready-made reference images and just captured image to be tested. This results in defects image only. In the third step, by extracting four features from each detected defect, followed by assigning them into the input nodes of an already trained artificial neural network we can obtain a defect class corresponding to the features. All of the image data are formed in a bit level for the reduction of data size as well as time saving. Experimental results show that proposed algorithms are found to be effective for flexible defect detection, robust classification, and high speed process by adopting a simple logic operation.

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Reducing False Alarms in Schizophrenic Parallel Synchronizer Detection for Esterel (Esterel에서 동기장치 중복사용 문제 검출시 과잉 경보 줄이기)

  • Yun, Jeong-Han;Kim, Chul-Joo;Kim, Seong-Gun;Han, Tai-Sook
    • Journal of KIISE:Software and Applications
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    • v.37 no.8
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    • pp.647-652
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    • 2010
  • Esterel is an imperative synchronous language well-adapted to control-intensive systems. When an Esterel program is translated to a circuit, the synchronizer of a parallel statement may be executed more than once in a clock; the synchronizer is called schizophrenic. Existing compilers cure the problems of schizophrenic parallel synchronizers using logic duplications. This paper proposes the conditions under which a synchronizer causes no problem in circuits when it is executed more than once in a clock. In addition we design a detection algorithm based on those conditions. Our algorithm detects schizophrenic parallel synchronizers that have to be duplicated in Esterel source codes so that compilers can save the size of synthesized circuits

Design and Performance Evaluation of Tactile Device Using MR Fluid (MR 유체를 이용한 촉감구현장치의 설계 및 성능 평가)

  • Kim, Jin-Kyu;Oh, Jong-Seok;Lee, Snag-Rock;Han, Young-Min;Choi, Seung-Bok
    • Transactions of the Korean Society for Noise and Vibration Engineering
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    • v.22 no.12
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    • pp.1220-1226
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    • 2012
  • This paper proposes a novel type of tactile device utilizing magnetorheological(MR) fluid which can be applicable for haptic master of minimally invasive surgery(MIS) robotic system. The salient feature of the controllability of rheological properties by the intensity of the magnetic field(or current) makes this potential candidate of the tactile device. As a first step, an appropriate size of the tactile device is designed and manufactured via magnetic analysis. Secondly, in order to determine proper input magnetic field the repulsive forces of the real body parts such as hand and neck are measured. Subsequently, the repulsive forces of the tactile device are measured by dividing 5 areas. The final step of this work is to obtain desired force in real implementation. Thus, in order to demonstrate this goal a neuro-fuzzy logic is applied to get the desired repulsive force and the error between the desired and actual force is evaluated.

Design of Digital Circuit Structure Based on Evolutionary Algorithm Method

  • Chong, K.H.;Aris, I.B.;Bashi, S.M.;Koh, S.P.
    • Journal of Electrical Engineering and Technology
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    • v.3 no.1
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    • pp.43-51
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    • 2008
  • Evolutionary Algorithms (EAs) cover all the applications involving the use of Evolutionary Computation in electronic system design. It is largely applied to complex optimization problems. EAs introduce a new idea for automatic design of electronic systems; instead of imagine model, ions, and conventional techniques, it uses search algorithm to design a circuit. In this paper, a method for automatic optimization of the digital circuit design method has been introduced. This method is based on randomized search techniques mimicking natural genetic evolution. The proposed method is an iterative procedure that consists of a constant-size population of individuals, each one encoding a possible solution in a given problem space. The structure of the circuit is encoded into a one-dimensional genotype as represented by a finite string of bits. A number of bit strings is used to represent the wires connection between the level and 7 types of possible logic gates; XOR, XNOR, NAND, NOR, AND, OR, NOT 1, and NOT 2. The structure of gates are arranged in an $m{\times}n$ matrix form in which m is the number of input variables.

Methods to Reduce Execution Time of Ontology Reasoners based on Tableaux Algorithm (태블로 알고리즘 기반 온톨로지 추론 엔진의 속도 향상을 위한 방법)

  • Kim, Je-Min;Park, Young-Tack
    • Journal of KIISE:Software and Applications
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    • v.36 no.2
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    • pp.153-160
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    • 2009
  • As size of ontology has been increased more and more, the descriptions in the ontologies become more complicated, Therefore finding and modifying unsatisfiable concepts is hard work in ontology construction process, Minerva is an ontology reasoner which detects unsatisfiable concepts automatically and infers subsumption relation between concepts in ontology, Most description logic based ontology reasoners (including Minerva) work using tableaux algorithm, Because tableaux algorithm is very costly, ontology reasoners need various optimization methods, In this paper, we propose optimizing methods to reduce execution time of tableaux algorithm based ontology reasoner. Proposed methods were applied to Minerva which was developed as preceding study result. In consequence the new version Minerva shows high performance.

SOC Verification Based on WGL

  • Du, Zhen-Jun;Li, Min
    • Journal of Korea Multimedia Society
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    • v.9 no.12
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    • pp.1607-1616
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    • 2006
  • The growing market of multimedia and digital signal processing requires significant data-path portions of SoCs. However, the common models for verification are not suitable for SoCs. A novel model--WGL (Weighted Generalized List) is proposed, which is based on the general-list decomposition of polynomials, with three different weights and manipulation rules introduced to effect node sharing and the canonicity. Timing parameters and operations on them are also considered. Examples show the word-level WGL is the only model to linearly represent the common word-level functions and the bit-level WGL is especially suitable for arithmetic intensive circuits. The model is proved to be a uniform and efficient model for both bit-level and word-level functions. Then Based on the WGL model, a backward-construction logic-verification approach is presented, which reduces time and space complexity for multipliers to polynomial complexity(time complexity is less than $O(n^{3.6})$ and space complexity is less than $O(n^{1.5})$) without hierarchical partitioning. Finally, a construction methodology of word-level polynomials is also presented in order to implement complex high-level verification, which combines order computation and coefficient solving, and adopts an efficient backward approach. The construction complexity is much less than the existing ones, e.g. the construction time for multipliers grows at the power of less than 1.6 in the size of the input word without increasing the maximal space required. The WGL model and the verification methods based on WGL show their theoretical and applicable significance in SoC design.

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Development of a Transcutaneous Optical Information Transmission System for Total Artificial Heart Using Near Infrared Laser

  • Lee, Jung-Hoon;Kim, Wook-Eun;Choi, Jong-Hoon;Ahn, Jae-Mok;Min, Byoung-Goo
    • Proceedings of the KOSOMBE Conference
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    • v.1997 no.05
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    • pp.64-67
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    • 1997
  • In the total artificial heart(TAH), a transcutaneous information transmission system(TITS) is vely important to monitor the TAH status and detect the device failure, and repair the possible problems. First of all, the communication channel(skin) and method were simulated in terms of transmittance, scattering, reflection and absorption, then the system was designed with size reduction including low power consumption and reliability compared to the previous one. The informations are transmitted through the skin(approximately 1cm in depth) by frequency modulated near infrared(NIR) pulses using 780nm laser diodes as transmitters and photodiode as receiver with high speed and high spectral sensitivity. The logic high and low frequencies are 3MHz, 1MHz respectively. The system is a bidirectional data link for more than 38.4Kbps data rate, full-duplex with a bit error rate of less than $10^{-5}$.

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