• 한국정보통신학회:학술대회논문집
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• 한국해양정보통신학회 2002년도 춘계종합학술대회
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• pp.518-522
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• 2002

This paper proposes a new application of Fuzzy logic to Variable Step Size Least Mean Square (VS-LMS) adaptive beamforming algorithm in CDMA systems. The proposed algorithm adjusts the step size of the Least Mean Square (LMS) by using the application of Fuzzy logic in which the increase or decrease of step size depends on the fuzzy inference results of the Mean Square Error (MSE). Computer simulation results show that the proposed algorithm has a better capacity of tracking compared with the conventional LMS algorithms and other variable step size LMS algorithms.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2003년도 ICCAS
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• pp.1066-1070
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• 2003

Recently technologies have created new principle and theory but the PID control system remains its popularity as the PID controller contains simple structure, including maintenance and parameter adjustment being so simple. Thus, this paper proposes auto tune PID by fuzzy logic controller based on FPGA which to achieve real time and small size circuit board. The digital PID controller design to consist of analog to digital converter which use chip TDA8763AM/3 (10 bit high-speed low power ADC), digital to analog converter which use two chip DAC08 (8 bit digital to analog converters) and fuzzy logic tune digital PID processor embedded on chip FPGA XC2S50-5tq-144. The digital PID processor was designed by fundamental PID equation which architectures including multiplier, adder, subtracter and some other logic gate. The fuzzy logic tune digital PID was designed by look up table (LUT) method which data storage into ROM refer from trial and error process. The digital PID processor verified behavior by the application program ModelSimXE. The result of simulation when input is units step and vary controller gain ($K_p$, $K_i$ and $K_d$) are similarity with theory of PID and maximum execution time is 150 ns/action at frequency are 30 MHz. The fuzzy logic tune digital PID controller based on FPGA was verified by control model of level control system which can control level into model are correctly and rapidly. Finally, this design use small size circuit board and very faster than computer and microcontroller.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 ITC-CSCC -1
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• pp.216-219
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• 2002

A novel approach of embedded systems for video coding is introduced with the main theme focused on logic-enhanced DRAM and configurable processor. This approach is aiming at reducing high computational costs and frequent memory accessing, which embedded systems are suffering with in the execution of video coding. According Co the software execution analysis, large size functions with intensive memory accesses are tuned to be executed by the logic-enhanced DRAM while small size functions repeatedly called are to be executed by dedicated instructions, which are newly introduced in the configurable processor. The proposed system can speed up H.263 video coding algorithm 7.4 times in comparison with the conventional embedded processor based system.

• 전자공학회논문지B
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• 제32B권6호
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• pp.868-875
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• 1995

This paper presents a method of constructing the multiple-valued combinational logic systems(MVCLS) by decision diagram. The switching function truth table of MVCLS is transformed into canonical normal form of sum-of-products(SOP) with literals at first. Next, the canonical normal form of SOP is transfered into multiple-valued logic decision diagram(MVLDD). The selecting of variable ordering is very important in this stage. The MVLDDs are quite different from each other according to the variable ordering. Sometimes the inadequate variable ordering produces a very large size of MVLDD means the large size of circuit implementation. An algorithm for generating the proper variable ordering produce minimal MVLDD and an example shows the verity of the algorithm. The circuits are realized with T-gate acceording to the minimal MVLDD.

• ETRI Journal
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• 제28권5호
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• pp.574-582
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• 2006

In this paper, a new error concealment algorithm is proposed for the H.264 standard. The algorithm consists of two processes. The first process uses a fuzzy logic method to select the size type of lost blocks. The motion vector of a lost block is calculated from the current frame, if the motion vectors of the neighboring blocks surrounding the lost block are discontinuous. Otherwise, the size type of the lost block can be determined from the preceding frame. The second process is an error concealment algorithm via a proposed adapted multiple-reference-frames selection for finding the lost motion vector. The adapted multiple-reference-frames selection is based on the motion estimation analysis of H.264 coding so that the number of searched frames can be reduced. Therefore the most accurate mode of the lost block can be determined with much less computation time in the selection of the lost motion vector. Experimental results show that the proposed algorithm achieves from 0.5 to 4.52 dB improvement when compared to the method in VM 9.0.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1988년도 전기.전자공학 학술대회 논문집
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• pp.579-581
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• 1988

This paper proposes the logic simulation for hierarchical logic network with function descriptor base data structure and algorithm on which a macro cell is considered as a logic elements. Function descriptor base data structure is useful when many logic elements of which type is same exist in a network, for it lessens the computer memory size used during the simulation. And the proposed simulation algorithm may improve the simulation speed.

• 대한전기학회논문지:전력기술부문A
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• 제48권12호
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• pp.1554-1563
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• 1999

This paper presents the design of high speed processor for a sequence logic control using field programmable gate array(FPGA). The sequence logic controller is widely used for automating a variety of industrial plants. The FPGA designed by VHDL consists of program and data memory interface block, input and output block, instruction fetch and decoder block, register and ALU block, program counter block, debug control block respectively. Dedicated clock inputs in the FPGA were used for high speed execution, and also the program memory was separated from the data memory for high speed execution of the sequence instructions at 40 MHz clock. Therefore it was possible that sequence instructions could be operated at the same time during the instruction fetch cycle. In order to reduce the instruction decoding time and the interface time of the data memory interface, an instruction code size was implemented by 16 bits or 32 bits respectively. And the real time debug operation was implemented for easy debugging the designed processor. This FPGA was synthesized by pASIC 2 SpDE and Synplify-Lite synthesis tool of Quick Logic company. The final simulation for worst cases was successfully performed under a Verilog HDL simulation environment. And the FPGA programmed for an 84 pin PLCC package was applied to sequence control system with inputs and outputs of 256 points. The designed processor for the sequence logic was compared with the control system using the DSP(TM320C32-40MHz) and conventional PLC system. The designed processor for the sequence logic showed good performance.

• 한국안전학회지
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• 제30권6호
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• pp.34-39
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• 2015

The study is aimed to develop fuzzy logic system that has overcurrent and saturation time as input variable and possibility of electrical fire as output variable by making bad conductor area with physical damage to indoor wiring. Most previous studies focused on thermal characteristics depending on the current size and no study considered the current size and saturation time at the same time. Therefore, the paper made into account current value and saturation time together. To this end, it created bad conductor area half the size of IV conductor (1.6 mm) on purpose and transmit electrical current from 10A to 60A by unit of 2A to find out the thermal characteristics and saturation time for current. Based on the data that came out, the study applied fuzzy logic and established the current and saturation time as input variable and chance of fire as output variable. As a result, the center of area of the system that depended only on the existing current value was 75 while the system that applied both current and saturation time presented the chance of fire at 92. It is found that the chance of bad conductor area and deteriorated insulation of electrical wire had current and saturation time as important variables. The data can be used as basic data like deteriorated wire insulation or operation features of circuit breaker in investigating the cause of electrical fire.

• 한국지반환경공학회 논문집
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• 제13권10호
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• pp.55-62
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• 2012

본 연구에서는 개별요소해석 프로그램인 $PFC^{3D}$를 이용하여 대입경 조립재료의 특정 입도분포를 구현하는 알고리즘을 개발하였다. 기존의 입자 형상이나 입도를 구현하기 위해 사용되었던 clump logic 또는 cluster logic을 사용하지 않으며 요소의 경계면 이탈 현상과 경계면 파괴 등을 방지할 수 있는 초기 개별요소 모델링 기법을 고안하였다. 최종적으로 대입경 조립재료에 대한 대형 삼축압축시험을 수치 모델링하고 실내시험 결과와 비교하였다. 해석 결과, 실제 시료의 입도분포와 매우 흡사한 분포의 개별요소를 생성할 수 있었고, 적정 미시물성치 산정 과정(calibration)을 통해 다양한 구속응력 조건에 대한 대입경 조립재료의 특정 입도분포하에서의 전체적인 수치 모델링이 가능하였다.

• 대한전자공학회논문지
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• 제23권1호
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• pp.42-45
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• 1986

This paper introduces novel functionally integrated logic elements which are conceptuallized for large scale integrated circuits. Efforts are made to minimize the gate size as well as to reduce the operational voltage, without sacrificing the speed performance of the gates. The process used was a rather conventional collector diffusion isolation(CDI) process. New gate structures are formed by merging several transistors of a gate in the silicon substrate. Thested elements are CML(Current Mode Logic) and EECL (Emitter-to-Emitter Coupled Logic)gates. The obtained experimental results are power-delay product of 6~11pJ and delay time/gate of 1.6~1.8 ns, confirming the possibility of these novel gate structures as a VLSI-candidate.