Simulation for hierarchical logic network

계층적 논리 회로의 시뮬레이션

This paper proposes the logic simulation for hierarchical logic network with function descriptor base data structure and algorithm on which a macro cell is considered as a logic elements. Function descriptor base data structure is useful when many logic elements of which type is same exist in a network, for it lessens the computer memory size used during the simulation. And the proposed simulation algorithm may improve the simulation speed.