• Journal of the Institute of Electronics Engineers of Korea TC
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• v.44 no.1
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• pp.69-78
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• 2007

A Frequency synthesizer for T-DMB and mobile-DTV applications was designed using $0.18{\mu}m$ CMOS process with 1.8V supply. PMOS transistors were chosen for VCO core to reduce phase noise. The VCO range is 920MHz-2100MHz using switchable inductors, capacitors and varactors. Varactor biases that improve varactor acitance characteristics were minimized as two, and $K_{VCO}$(VCO gain) value was aintained by switchable varactor. Additionally, VCO was designed that VCO gain and the interval of VCO gain were maintained using VCO gain compensation logic. VCO, PFD, CP and LF were verified by Cadence Spectre, and divider was simulated using Matlab Simulink, ModelSim and HSPICE. VCO consumes 10mW power, and is 56.3% tuning range. VCO phase noise is -127dBc/Hz at 1MHz offset for 1.58GHz output frequency. Total power consumption of the frequency synthesizer is 18mW, and lock time is about $140{\mu}s$.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.20 no.3
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• pp.53-61
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• 2006

This paper is proposed adaptive fuzzy-neuro controller for high performance of induction motor drive. The design of this algorithm based on fuzzy-neural network controller that is implemented using fuzzy control and neural network. This controller uses fuzzy nile as training patterns of a neural network. Also, this controller uses the back-propagation method to adjust the weights between the neurons of neural network in order to minimize the error between the command output and actual output. A model reference adaptive scheme is proposed in which the adaptation mechanism is executed by fuzzy logic based on the error and change of error measured between the motor speed and output of a reference model. The control performance of the adaptive fuzzy-neuro controller is evaluated by analysis for various operating conditions. The results of experiment prove that the proposed control system has strong high performance and robustness to parameter variation, and steady-state accuracy and transient response.

• The Transactions of the Korea Information Processing Society
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• v.1 no.3
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• pp.299-310
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• 1994

Re-engineering tools can substantially increase software maintenance productivity and the quality of maintenance work. Re-engineering usually involves changing the form(e.g.changining objects names and definitions, restructuring process logic) of a program. In this paper, we describe the design and implementation of InMaC＋＋ that is a software tool oriented towards maintenance of C＋＋ object oriented programs. With InMaC＋＋, programms can be displayed and edited in two forms : as the code and as the diagram InMaC＋＋ also contains transformations in both directions, i,e. from code to diagram and from diagram to skeletons of code. Hence, it is suitable for re-engineering and maintenance of existing code. Specially designed browsers implement the graphical interface. InMaC＋＋ contains a database that is based on a simple but effective data model of InMaC＋＋ programs. The model contains only four object classes and three relations, which makes the tool small, and easy to implement and use. A simple query language allows browsing through the database.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.23 no.8
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• pp.2064-2071
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• 1998

A new digital clock level translator has been designed in order to produce a clock source of the internal logic circuits. The translator output has 50% duty ratio from small sinusoidal input such as TCXO which oscillates itself in poratable components. The circuit consists of positive and negative comparators, RS latch, charge pump, and reference vol- tage generator. It detects pulse width of the output waveform and feedbacks the control signal to the input com-parator. It detects pulse width of the output waveform and feedbacks the control signal to the input com-parator reference, producing output waveform with valid 50% duty ratio of the digital signal level. The designed level translator can be used as a sampling clock source of ADC, PLL and the colck source of the clock synthesizer. The circuit wasdesigned in a 0.8.mu.m analog CMOS technology with double metal, double poly, and BSIM3 circuit simulation model. From our experimental results, a stable operating characteristics of 50 +3% duty ratio was obtained from the sinusoidal input wave of 370 mV.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.11
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• pp.57-65
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• 2014

This paper presents a framework that is based on a reconfigurable macro-model of current-mode logic (CML) high-speed digital circuits enabling equation-based design optimization. The proposed macro-model is compatible with geometric programming, thereby enabling constraint-driven top-level power optimization. The proposed optimization framework is applied to a design of CML based serial-link transmitter with user-defined design specifications as an example of high speed digital circuits using 45nm and 90nm CMOS technology. The proposed optimization framework can derive a design with optimal power efficiency for given transistor technology nodes.

• Journal of IKEEE
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• v.20 no.3
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• pp.260-264
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• 2016

The MAX77846, which is compatible with MAX77826, is a sub-power management IC (PMIC) for the latest Wearable Watch and 3G/4G smart phones. The MAX77846 contains N-MOSFET (N channel Metal-Oxide Semiconductor Field-Effect Transistor), a high-efficiency regulator, and comparator, etc to power up peripherals. The MAX77846 also provides power on/off control logic for complete flexibility and an $I^2C$ (Inter Integrated Circuit) serial interface to program individual regulator output voltages. In this paper, the simplified power macro-model based on MAX77846 is designed to verify the performance of the battery voltage in terms of current and time, and simulated by using of the LTspice. In addition, it is verified how much time can the charged battery capacity for Samsung Galaxy Gear 2 be used to operate a specified function after measuring the currents flowing to carry out the main functions in real time, which will be applicable to design parameters for the advanced power module

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.53 no.8
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• pp.561-570
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• 2004

In this paper, new architectures and comprehensive design methodologies of Genetic Algorithms(GAs) based Genetically optimized Neurofuzzy Networks(GoNFN) are introduced, and a series of numeric experiments are carried out. The proposed GoNFN is based on the rule-based Neurofuzzy Networks(NFN) with the extended structure of the premise and the consequence parts of fuzzy rules being formed within the networks. The premise part of the fuzzy rules are designed by using space partitioning in terms of fuzzy sets defined in individual variables. In the consequence part of the fuzzy rules, three different forms of the regression polynomials such as constant, linear and quadratic are taken into consideration. The structure and parameters of the proposed GoNFN are optimized by GAs. GAs being a global optimization technique determines optimal parameters in a vast search space. But it cannot effectively avoid a large amount of time-consuming iteration because GAs finds optimal parameters by using a given space. To alleviate the problems, the dynamic search-based GAs is introduced to lead to rapidly optimal convergence over a limited region or a boundary condition. In a nutshell, the objective of this study is to develop a general design methodology o GAs-based GoNFN modeling, come up a logic-based structure of such model and propose a comprehensive evolutionary development environment in which the optimization of the model can be efficiently carried out both at the structural as well as parametric level for overall optimization by utilizing the separate or consecutive tuning technology. To evaluate the performance of the proposed GoNFN, the models are experimented with the use of several representative numerical examples.

• Journal of the Korean Institute of Intelligent Systems
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• v.19 no.5
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• pp.689-694
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• 2009

In this paper an approach to building fuzzy models for predicting daily and weekly stock prices is presented. Predicting stock prices with traditional time series analysis has proven to be difficult. Fuzzy logic based models have advantage of expressing the input-output relation linguistically, which facilitates the understanding of the system behavior. In building a stock prediction model we bear a burden of selecting most effective indicators for the stock prediction. In this paper information used in traditional candle stick-chart analysis is considered as input variables of our fuzzy models. The fuzzy rules have the premises and the consequents composed of trapezoidal membership functions and nonlinear equations, respectively. DE(Differential Evolution) identifies optimal fuzzy rules through an evolutionary process. The fuzzy models to predict daily and weekly open, high, low, and close prices of KOSPI(KOrea composite Stock Price Index) are built, and their performances are demonstrated.

• Korean Journal of Labor Studies
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• v.24 no.1
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• pp.261-295
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• 2018

This study draws on data from the 1st (2005) to 6th (2015) waves of the Workplace Panel Survey regarding workplaces with labor representatives, i.e., a trade union or labor-management council, and analyzes these using a fixed effects panel data model to examine the relationship between the level of worker participation and the economic performance of workplaces. Analysis results indicate that higher levels of worker participation in an earlier time period are associated with higher per-worker value added (productivity) and per-worker labor costs (wages) at the current time period, but only up to a certain level beyond which the effect is found to decrease, thus forming an inverted-U shape pattern. Considered from a broad framework, these results are in line with the theoretical predictions by Freeman and Lazear (1995), who had established the logic behind the dynamics of the participation of labor representatives in management activities. In view of the fact that the current average level of worker participation in Korea is very low, the empirical analysis results of this study presents the policy implication that raising the level of workplace participation somewhat beyond current levels would yield improvements in economic performance in terms of the shared rent between labor and management - i.e., productivity (per-worker value added).

• Advances in nano research
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• v.7 no.3
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• pp.209-221
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• 2019

Graphene, with impressive electronic properties, have high potential in the microelectronic field. However, graphene itself is a zero bandgap material which is not suitable for digital logic gates and its application. Thus, much focus is on graphene nanoribbons (GNRs) that are narrow strips of graphene. During GNRs fabrication process, the occurrence of defects that ultimately change electronic properties of graphene is difficult to avoid. The modelling of GNRs with defects is crucial to study the non-idealities effects. In this work, nearest-neighbor tight-binding (TB) model for GNRs is presented with three main simplifying assumptions. They are utilization of basis function, Hamiltonian operator discretization and plane wave approximation. Two major edges of GNRs, armchair-edged GNRs (AGNRs) and zigzag-edged GNRs (ZGNRs) are explored. With single vacancy (SV) defects, the components within the Hamiltonian operator are transformed due to the disappearance of tight-binding energies around the missing carbon atoms in GNRs. The size of the lattices namely width and length are varied and studied. Non-equilibrium Green's function (NEGF) formalism is employed to obtain the electronics structure namely band structure and density of states (DOS) and all simulation is implemented in MATLAB. The band structure and DOS plot are then compared between pristine and defected GNRs under varying length and width of GNRs. It is revealed that there are clear distinctions between band structure, numerical DOS and Green's function DOS of pristine and defective GNRs.