• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.1021-1024
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• 1998

Computer-aided design of VLSI circuits is usually carried out in three synthesis steps; high-level synthesis, logic synthesis and layout synthesis. Each synthesis step is further kroken into a few optimization problems. In this paper we study the area minimization problem in floorplanning(also known as the floorplan sizing problem). We propose the area minimization algorithms for general floorplans.

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 1993.06a
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• pp.785-788
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• 1993

This paper presents the prototype framework for automated integration of CMOS current-mode fuzzy logic circuits using an intelligent module approach. The library of modules representing the standard fuzzy logic operators was built. These modules were finally used to synthesized sophisticated fuzzy logic units. Fuzzy unit designs were made based upon the results of a newel methodology of the current mirror-based fuzzy logic function synthesis. This methodology is actually incorporated into the presented framework. As an example, the membership function unit was synthesized, simulated, and the final layout was generated using the presented framework. Finally, the fuzzy logic controller unit (FLC) was generated using the proposed framework. Simulation as well as measurement results show unquestionable advantages of the proposed fuzzy logic function integration system over the classical design methodology with respect to the area, relative error and performance.

• The Transactions of the Korea Information Processing Society
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• v.3 no.3
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• pp.640-654
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• 1996

This paper presents a synthesis method for multi-level Reed-Muller circuits using BDDs(Binary Decision Diagrams). The existing synthesis tool for Reed circuits, FACTOR, is not appropriate to the synthesis of large circuits because it uses matrix (map-type) to represent given logic functions, resulting in the exponential time and space in number of imput to the circuits. For solving this problems, a syntheisis method based on BDD is presented. Using BDDs, logic functions are represented compactly. Therefor storage spaces and computing time for synthesizing logic functions were greatly decreased, and this technique can be easily applied to large circuits. Using BDD representations, the proposed method extract best patterns to minimize multi-level Reed Muller circuits with good performance in area optimization and testability. Experimental results using the proposed method show better performance than those using previous methods〔2〕. For large circuits of considering the best input partition, synthesis results have been improved.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.29A no.4
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• pp.64-73
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• 1992

This paper presents the design of multi-level logic optimization algorithm and the development of the SMILE system based on the algorithm. Considering the fanin constraints in algorithmic level, SMILE performs global and local optimization in a predefined sequence using heuristic information. Designed under the Sogang Silicon Compiler design environment, SMILE takes the SLIF netlist or Berkeley equation formats obtained from high-level synthesis process, and generates the optimized circuits in the same format. Experimental results show that SMILE produces the promising results for some circuits from MCNC benchmarks, comparable to the popularly used multi-level logic optimization system, MIS.

• Proceedings of the IEEK Conference
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• 1998.06a
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• pp.883-886
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• 1998

We introduce a high level synthesis methodlogoy for automatic synthesis of asynchronous circuits form a language based on CSP. The input language is a high level concurrent algorithmic specification that can model complex concurrent control flow, logical and arithmetic computation and communications between them. This specification is translated into petri net which has actions. These actions are refined to synthesize the controllers and to allocate the data resources. We use the automatic synthesis through signal transition graphs (STGs) that allows to take advantage of logic synthsis methods to optimize the circuit.

• Journal of the Institute of Convergence Signal Processing
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• v.6 no.3
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• pp.134-142
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• 2005

The implementation of Multiple-Valued Logic(MVL) based on Current-Mode CMOS Logic(CMCL) circuits has recently been achieved. In this paper, four-valued Unary Multiple-Valued logic functions are synthesized using current-mode CMOS logic circuits. We properly make use of the fact that the CMCL addition of logic values represented using discrete current values can be performed at no cost and that negative logic values are readily available via reversing the direction of current flow. A synthesis process for CMCL circuits is based upon a logically complete set of basic elements. Proposed algorithm results in less expensive realization than those achieved using existing techniques in terms of the number of transistors needed. As an alternative to the cost-table techniques Universal Unary Programmable Circuit (UUPC) for a unary function is also proposed.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.18 no.8
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• pp.361-366
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• 2017

For two given logical expressions and, when expression contains the same part of the logical expression as expression, substituting for that part of expression is called a substituted logic expression. If a substituted relation is established between the logical expressions, there is an advantage in that the number of literals used in the whole logical expression can be greatly reduced. However, if the substituted relation is not established, there is no simplification effect obtained from the substituted expression. Previous methods proposed a way to find substituted relations between logical expressions for the given logical expressions themselves, and to calculate substituted expressions if only substitution is possible. In this paper, a new method for performing substitution with addition and revision of logic terms is proposed in order to perform substitution, even though there is no substituted relation between two logic expressions. The proposed method is efficiently implemented using a matrix that finds terms to be added. Then, by covering the matrix that has added terms, substituted logic expressions are found. Experiment results show that the proposed method for several benchmark circuits can reduce the number of literals, compared to existing synthesis tools.

• Journal of the Korean Institute of Telematics and Electronics
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• v.21 no.6
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• pp.56-63
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• 1984

This paper proposes a programmed logic realization of sequential logic system with parallel sequences which is described by a GRAFCET. For this purpose, an algorithm is proposed, which decomposes the GRAFCET with parallel sequence into a set of state graph without changing the physical meaning, which is applied to all kinds of GRAFCET, and which divides the system into sub-systems and vice versa. A systematic implementation by microprogrammed logic using ROM is proposed, which expands the number of selection sequence.

• 전기의세계
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• v.28 no.1
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• pp.43-52
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• 1979

Recently, interest in multivalued(MV) logic system has been increased, despites the apparent difficulties for practical application. This is because of the many advantages of the MV compared with the 2-valued logic systems, such as; (a) higher speed of arithmetical operation on account of the smaller number of digits required for a given data, (b) better utilization of data transmission channels on account of the higher information contents per line, (c) potentially higher density of information storage. This paper describes a MV switching theory and experimental MV logic elements based on current-mode logic technique. These elements tried were a 3-stable pulse generator, a ternary AND, a ternary OR, a MT circuit and a ternary inverter. Tristable flops which are indispensable for constituting a ternary shift register are synthesized using these gates. A BCD to TCD decoder, and vice versa, are proposed by using a ternary inverter and some binary gates. Thus, the feasibility of a large scale MV digital system has been demonstrate.

• The KIPS Transactions:PartA
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• v.9A no.3
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• pp.351-362
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• 2002

Along with an asynchronous finite state machine, in short AFSM, a signal transition graph, in short STG, is one of the most widely used behavioral description languages for asynchronous controllers. Unfortunately, STGs are not user-friendly, and thus it is very unwieldy and time consuming for system designers to conceive and describe manually the behaviors of a number of asynchronous controllers which constitute an asynchronous control unit for a target system in the form of STGs. In this paper, we suggest an automatic STG derivation method through a process-oriented method. Since the suggested method considers special properties of STG-based asynchronous logic synthesis very carefully, asynchronous controllers which are synthesized from STGs derived through the suggested method are superior in aspects of area, synthesis time, performance and implementability compared to those obtained through previous methods.