• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.1
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• pp.69-78
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• 2010

To implement the high performance SoC, we propose the flying master bus architecture that a specially defined master named as the flying master directly accesses the selected slaves with no regard to the bus protocol. The proposed bus architecture was implemented through Verilog and mapped the design into Hynix 0.18um technology. As master and slave wrappers have around 150 logic gate counts, the area overhead is still small considering the typical area of modules in SoC designs. In TLM performance simulation about proposed architecture, 25~40% of transaction cycle and 43~60% of bus efficiency are increased and 43~77% of request cycle is decreased, compared with conventional bus architecture. Conclusively, we assume that the proposed flying master bus architecture is promising as the leading candidate of the bus architecture in the aspect of performance and efficiency.

• Journal of Advanced Navigation Technology
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• v.22 no.5
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• pp.429-435
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• 2018

In radar systems, FFT (fast Fourier transform) operation is necessary to obtain the range and velocity of target, and the design of an FFT processor which operates at high speed is required for real-time implementation. The perfect shuffle network is suitable for high-speed FFT processor. In particular, twice perfect shuffle network based on radix-4 is preferred for very high-speed FFT processor. Moreover, radar systems that requires various velocity resolution should support scalable FFT points. In this paper, we propose a 8~1024-point scalable FFT processor based on twice perfect shuffle network algorithm and present hardware design and implementation results. The proposed FFT processor was designed using hardware description language (HDL) and synthesized to gate-level circuits using $0.65{\mu}m$ CMOS process. It is confirmed that the proposed processor includes logic gates of 3,293K.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.31 no.10
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• pp.89-96
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• 2003

In this paper, a CCSDS(Consultative Committee for Space Data Systems) telecommand(TC) decryptor for the security of geostationary communications satellite was implemented. For the confidentiality of CCSDS TC datalink security, Option-A which implements the security services below the transfer sublayer was selected. Also CFB(Cipher Feedback) operation mode of DES(Data Encryption Standard) was used for the encryption of 56-bit data bits in 64-bit codeblock. To verify Decryptor function, the DES CFB logic implemented on A54SX32 FPGA(Field Programmable Gate Array) was integrated with interface and control logics in a PCB(Printed Circuit Board). Using a function test PC, the encrypted codeblocks were generated, transferred into the decryptor, decrypted, and the decrypted codeblocks were transmitted to the function test PC, and then compared with the source codeblocks. Through LED(Light Emitting Diode) ON operation by driving the relay related to Op-code decoded and the comparison between the codeblock output waveforms measured and those simulated, the telecommand decryptor function was verified.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.34 no.1
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• pp.110-115
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• 2006

STSAT-2 is the first satellite which will be launched by the first Korean Space Launch Vehicle(KSLV). Ground station Baseband Control system(GBC) is now developed for STSAT-2. GBC has two functions. One is control data path between satellite control computers and ground station antennas(1.5M, 3.7M, 13M) automatically. The other is sending and receiving data between ground station and satellite. GBC is implemented by FPGA(Field-Programmable Gate Array) which includes almost all logic(for MODEM, PROTOCOL and GBC system control). MODEM in GBC has two uplink FSK modulators(1.2[kbps], 9.6[kbps]) and six downlink FSK demodulators(9.6[kbps], 38.4[kbps]). In hardware, STSAT-2 GBC is smaller than STSAT-1 GBC. In function, STSAT-2 GBC has more features than STSAT-1 GBC. This paper is about GBC structure, functions and test results.

• ETRI Journal
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• v.37 no.6
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• pp.1143-1153
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• 2015

In this paper, we propose an efficient architecture for a real-time image stitching engine for vision SoCs found in motor vehicles. To enlarge the obstacle-detection distance and area for safety, we adopt panoramic images from multiple telegraphic cameras. We propose a stitching method based on a fixed homography that is educed from the initial frame of a video sequence and is used to warp all input images without regeneration. Because the fixed homography is generated only once at the initial state, we can calculate it using SW to reduce HW costs. The proposed warping HW engine is based on a linear transform of the pixel positions of warped images and can reduce the computational complexity by 90% or more as compared to a conventional method. A dual-core SW/HW image stitching engine is applied to stitching input frames in parallel to improve the performance by 70% or more as compared to a single-core engine operation. In addition, a dual-core structure is used to detect a failure in state machines using rock-step logic to satisfy the ISO26262 standard. The dual-core SW/HW image stitching engine is fabricated in SoC with 254,968 gate counts using Global Foundry's 65 nm CMOS process. The single-core engine can make panoramic images from three YCbCr 4:2:0 formatted VGA images at 44 frames per second and frequency of 200 MHz without an LCD display.

• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.11
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• pp.135-143
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• 1990

A new over-the-cell routing system is proposed in this paper. The proposed system efficiently reduces not only the channel density but also the routing density in cell region. Generally, the over-the-cell system consists of three phases. Namely, over-the-cell routing, terminal selection and channel routing. In this paper, to select the nets to be routed over the cells, weights are assigned on the intersection graph considering both the channel density and the intersection relations among other nets. When selected nets are blocked by feedthroughs or metal layers for internal logic, they are routed by maze algorithm. Also, in order to reduce channel density, the terminals to be routed in a channel are selected using the minimum weight spanning tree. Channel routing is carried out with a channel router of HAN-LACAD_G. The effectiveness of the over-the-cell routing system is shown by the experiments with benchmark data and its application to the gate array layout system.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.7 s.361
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• pp.45-53
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• 2007

In this paper, we propose an efficient hardware architecture for H.264/AVC CAVLC (Context-based Adaptive Variable Length Coding) encoding. Previous CAVLC architectures search all of the coefficients to find statistic characteristics in a block. However, it is unnecessary information that zero coefficients following the last position of a non-zero coefficient when CAVLC encodes residual coefficients. In order to reduce this unnecessary operation, we propose two techniques, which detect the first and last position of non-zero coefficients and arrange non-zero coefficients sequentially. By adopting these two techniques, the required processing time was reduced about 23% compared with previous architecture. It was designed in a hardware description language and total logic gate count is 16.3k using 0.18um standard cell library Simulation results show that our design is capable of real-time processing for $1920{\times}1088\;30fps$ videos at 81MHz.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.7C
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• pp.712-722
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• 2002

We have investigated a novel optical decoder for a fiber-optic code division multiple access(CDMA) communication systems. The conventional optical encoder and decoder have the advantage of simple structure. However the number of users in the system is limited by the auto- and cross-correlation properties generated in decoding process. In previous studies, to improve the system performance, although they used an optical code that minimize the sidelobe and cross-correlation, could not yet find a novel methods for performance improvement in fiber-optic CDMA system. Thus, it is necessary to investigate the novel optical decode in order to improve the performance of system. In this paper, we schematize the AND gate logic element(AGLE) composed with 1$\times$2 or 1$\times$3 coupler and the optical thyristor and propose the novel optical decoder using K(weight) AGLE. The optical thyristor only passes the overlapped signal and clips other signals. Such a novel concept means that the optical thyristor can operate as a hard-limiter. We analyze the fiber-optic CDMA system using the novel optical decoder with simulation and is found that the novel optical decoder using the AGLE and optical thyristor excludes the sidelobe and cross-correlation intensity between any two sequences.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.2A
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• pp.129-136
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• 2005

A multiplier generator, VPM_Gen (Variable-Precision Multiplier Generator), which generates Verilog-HDL models of multiplier cores with user-defined bit-width specification, is described. The bit-widths of operands are parameterized in the range of $8-bit{\sim}32-bit$ with 1-bit step, and the product from multiplier core can be truncated in the range of $8-bit{\sim}64-bit$ with 2-bit step, resulting that the VPM_Gen can generate 3,455 multiplier cores. In the case of truncating multiplier output, by eliminating the circuits corresponding to the truncation part, the gate counts and power dissipation can be reduced by about 40% and 30%, respectively, compared with full-precision multiplier. As a result, an area-efficient and low-power multiplier core can be obtained. To minimize truncation error, an adaptive error-compensation method considering the number of truncation bits is employed. The multiplier cores generated by VPM_Gen have been verified using Xilinx FFGA board and logic analyzer.

• Journal of Communications and Networks
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• v.13 no.5
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• pp.481-493
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• 2011

Multiple-input multiple-output (MIMO) technology provides high data rate and enhanced quality of service for wireless communications. Since the benefits from MIMO result in a heavy computational load in detectors, the design of low-complexity suboptimum receivers is currently an active area of research. Lattice-reduction-aided detection (LRAD) has been shown to be an effective low-complexity method with near-maximum-likelihood performance. In this paper, we advocate the use of systolic array architectures for MIMO receivers, and in particular we exhibit one of them based on LRAD. The "Lenstra-Lenstra-Lov$\acute{a}$sz (LLL) lattice reduction algorithm" and the ensuing linear detections or successive spatial-interference cancellations can be located in the same array, which is considerably hardware-efficient. Since the conventional form of the LLL algorithm is not immediately suitable for parallel processing, two modified LLL algorithms are considered here for the systolic array. LLL algorithm with full-size reduction-LLL is one of the versions more suitable for parallel processing. Another variant is the all-swap lattice-reduction (ASLR) algorithm for complex-valued lattices, which processes all lattice basis vectors simultaneously within one iteration. Our novel systolic array can operate both algorithms with different external logic controls. In order to simplify the systolic array design, we replace the Lov$\acute{a}$sz condition in the definition of LLL-reduced lattice with the looser Siegel condition. Simulation results show that for LR-aided linear detections, the bit-error-rate performance is still maintained with this relaxation. Comparisons between the two algorithms in terms of bit-error-rate performance, and average field-programmable gate array processing time in the systolic array are made, which shows that ASLR is a better choice for a systolic architecture, especially for systems with a large number of antennas.