• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.22 no.1
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• pp.7-11
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• 2009

In this study, p-channel silicon-oxide-nitride-oxide-silicon(SONOS) transistors are fabricated and characterized as an unit cell for NAND flash memory. The SONOS transistors are fabricated by $0.13{\mu}m$ low power standard logic process technology. The thicknesses of gate insulators are 2.0 nm for the tunnel oxide, 1.4 nm for the nitride layer, and 4.9 nm for the blocking oxide. The fabricated SONOS transistors show low programming voltage and fast erase speed. However, the retention and endurance of the devices show poor characteristics.

• Proceedings of the Korean Society Of Semiconductor Equipment Technology
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• 2003.12a
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• pp.42-44
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• 2003

최근 logic 소자의 gate oxide로 기존의 $SiO_2$, SiON보다 고유전, 작은 누설전류를 가지는 물질의 개발이 중요한 이슈가 되고 있다. 본 실험실에서는 Si 기판위에 $HfO_2$ 를 바로 증착하는 경우, 기판의 Si 이박막내로 확산하여 유전율이 저하되는 문제점을 인식하고, 기판과 $HfO_2$ 사이에 $AlO_x$를 방지막으로 사용하였다. 이 때, $AlO_x$의 Al precursor 는 TMA 로 고정하고, 산화제로는 $H_2O, O_2$-plasma, O_3$ 를 각각 사용하였다. 모든 $AlO_x/HfO_y$ 박막에서 매우 우수한 누설전류특성을 얻을 수 있었는데, 특히 $O_3$ 를 산화제로 사용한 $AlO_x$ 방지막의 경우 가장 우수한 특성을 보였다. 또한 질소 분위기에서 $800^{\circ}C$ 10 분간 열처리한 후, 방지막을 사용한 모든 경우에서 보다 향상된 열적 안정성을 관찰할 수 있었다.

• Journal of the Optical Society of Korea
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• v.18 no.1
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• pp.65-70
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• 2014

This paper presents the simulation and design of an all-optical subtractor using a quantum-dot semiconductor optical amplifier Mach-Zehnder interferometer (QD-SOA MZI) structure consisting of two cascaded switches, the first of which produces the differential bit. Then the second switch produces the borrow bit by using the output of the first switch and the subtrahend data stream. Simulation results were obtained by solving the rate equations of the QD-SOA. The effects of QD-SOA length, peak power and current density have been investigated. The designed gate can operate at speeds of over 250 Gb/s. The simulation results demonstrate a high extinction ratio and a clear and wide-opening eye diagram.

• Proceedings of the IEEK Conference
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• 2000.07b
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• pp.1005-1008
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• 2000

This paper presents a simple method to estimate short-circuit power dissipation and propagation delay for static CMOS logic circuits. Short-circuit current expression is derived by accurately interpolating peak points of actual current curves which is influenced by the gate-to-drain coupling capacitance. The macro model and its expressions estimating the delay of CMOS circuits, which is based on the current modeling expression, are also proposed after investigating the voltage waveforms at transistor output modes. It is shown through simulations that the proposed technique yields better accuracy than previous methods when signal transition time and/or load capacitance decreases, which is a characteristic of the present technological evolution.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.32B no.11
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• pp.1434-1444
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• 1995

Current test has recently been known to be a promising testing method in CMOS VLSI because conventional voltage test can not make sure of the complete detection of bridging, gate-oxide shorts, stuck-open faults and etc. This paper presents a new BIC(built-in current sensor) for the internal current test in CMOS logic circuit. A single phase clock is used in the BIC to reduce the control circuitry of it and to perform a self- testing for a faulty current. The BIC is designed to detect the faulty current at the end of the clock period, so that it can test the CUT(circuit under test) with much longer critical propagation delay time and larger area than conventional BICs. The circuit is composed of 18 devices and verified by using the SPICE simulator.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.6
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• pp.22-27
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• 1997

This paper propose a novel VLSI architecture for a multiplierless FIR filter chip providing variable-length taps. To change the number of taps, we propose two special features called a data-reuse structure and a recurrent-coefficient scheme. These features consist of several MUXs and registers and reduce the number of gates over 20% compared with existing chips using an address generation unit and a modulo unit. Since multipliers occupy large VLSI area, a multiplierless filter chip meeting real-time requirement can save large area. We propose a modified bit-serial multiplication algorithm to compute two partial products in parallel, and thus, the proposed filter is twice faster and has smaller hardware than previous multiplierless filters. We developed VHDL models and performed logic synthesis using the 0.8.mu.m SOG (sea-of-gate) cell library. The chip has only 9,507 gates, was fabricated, and is running at 77MHz.

• Journal of Magnetics
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• v.14 no.1
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• pp.23-26
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• 2009

Spin injection from a ferromagnet into an n-doped $In_{0.53}Ga_{0.47}As$ channel was electrically detected by a ferromagnetic detector. At T = 20 K, using non-local and local spin-valve measurements, a non-local signal of $2\;{\mu}V$ and a local spin valve signal of 0.041% were observed when the bias current was 1 mA. The band calculation and Shubnikov-de Haas oscillation measurement in a bulk channel showed that the gate controlled spin-orbit interaction was not large enough to control the spin precession but it could be a worthy candidate for a logic device using spin accumulation and diffusion.

• Nuclear Engineering and Technology
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• v.48 no.2
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• pp.470-481
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• 2016

Field-programmable gate arrays (FPGAs) have received much attention from the nuclear industry as an alternative platform to programmable logic controllers for digital instrumentation and control. The software aspect of FPGA development consists of several steps of synthesis and refinement, and also requires verification activities, such as simulations that are performed individually at each step. This study proposed an integrated software-testing framework for simulating all artifacts of the FPGA software development simultaneously and evaluating whether all artifacts work correctly using common oracle programs. This method also generates a massive number of meaningful simulation scenarios that reflect reactor shutdown logics. The experiment, which was performed on two FPGA software implementations, showed that it can dramatically save both time and costs.

• Proceedings of the Optical Society of Korea Conference
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• 2000.08a
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• pp.20-21
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• 2000

광을 기반으로 한 논리 연산은 전자 소자의 속도 한계 및 연산 용량의 한계를 극복할 대안으로 많은 관심을 끌고 있다. 초고속 전광 논리 연산의 구현은 대부분 물질의 비선형성을 이용하며 특히 광섬유의 비선형 Ken 효과를 이용한 Sagnac 간섭계의 형태를 이용한 논리 연산이 주로 연구되어 왔다$^{(1)}$ . 그러나 광섬유의 비선형성을 이용하기 위해서는 충분히 큰 광 강도가 필요하며 회로 구성에 있어서도 크기가 크다는 단점이 있다. 최근에는 반도체 광증폭기의 비선형 이득 포화 현상을 이용한 TOAD 등이 발표되어 상대적으로 크기도 감소하고 사용되는 광 강도 역시 감소시킬 수 있었다$^{(2)}$ . 간섭계를 이용한 광논리의 구현은 Sagnac 간섭계 뿐만 아니라 비선형 특성을 갖는 도파로로 구성된 Mach-Zehnder 간섭계, Michelson 간섭계 등도 이용이 가능하다. (중략)

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2005.10a
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• pp.212-215
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• 2005

The needs of larger screen in mobile device would be increased as the time of ubiquitous and convergence is coming. And, the type of mobile device has been evolved from bar, slide to row. Recently, the study on the multi-display screen which has seamless gap between two display panel has been published, and moreover the System On Chip(SOC) design strategy of core chip has been the most promising Field-Programmable Gate Array(FPGA) technology in the display system. Therefore, in this paper, we proposed the design technique of SOC and evaluated the effectiveness with Very high speed Hardware Description Language(VHDL) Intellectual Property (IP) for the operation of multi display device driver. Also, This IP design would be to allow any kind of user interface in control system.