• Journal of the Korean Institute of Telematics and Electronics B
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• v.31B no.4
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• pp.55-61
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• 1994

The multiple valued logic(MVL) circuit with ROM type using current mode CMOS is presented in this paper. This circuit is composed of the multiple valued-to-binary(MV/B) decoder and the selection circuit. The MV/B decoder decodes the single input multiple valued signal to N binary signal, and the selection circuits is composed N$\times$N array of the selecion cells with ROM types. The selection cell is realized with the current mirror circuits and the inhibit circuits. The presented circuit is suitable for designing the circuit of MVL functions with independent variables, and reduces the number of selection cells for designing the circuit of symmetric MVL functions as many as {($N^2$-N)/2}+N. This circuit possess features of simplicity. expansibility for array and regularity, modularity for the wire routing. Also, it is suitable for VLSI implementation.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.1
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• pp.59-64
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• 2008

In this paper, we developed an virtual lecture to study digital logic circuits. The contents is intended fer the students without or with little knowledge about electrics or electronics. For the beginners, the lecture contains the basic electronics and basic circuit theory as well as the degital logic circuits to be more practical lecture. And we developed the virtual circuit lab which uses real-like devices, circuits and interactive objects for the students to experience practical digital circuits. With the features described above, this contents would be useful for the beginners who want to studying digital logic circuits.

• Journal of Practical Engineering Education
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• v.16 no.4
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• pp.481-489
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• 2024

The purpose of this study is to propose a new teaching method of the digital logic circuit so that students can cultivate digital literacy in diversifying future educational environments. In this paper, we analyzed the previous studies related to teaching methods for Tinkercad and digital logic circuits and suggested how to apply Tinkercad to the specific instruction design of the digital logic circuit. In addition, after showing the class design using Tinkercad to the actual lessons, It turns out two significant facts in a survey: to create a circuit that can implement the operation of the basic gate and to make it easier to understand the principles of the basic gate. The teaching method suggested in this study can be informative for students to acquire basic knowledge of electricity and electronics. Since Tinkercad is an open software based on cloud systems that are used not only in Korea but also foreign countries, it can be utilized in the lessons of digital logic circuits in the near future.

• Proceedings of the KIEE Conference
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• 2000.11d
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• pp.778-780
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• 2000

The 74181 is arithmetic logic units(ALU)/function generator. This circuit performs 16 binary arithmetic operations on two 4-bit words. And a full carry look-ahead scheme is made available in this device. The 74181 can also be utilized as a comparator. This circuit has been also designed to provide 16 possible functions of two Boolean variables without the use of external circuitry. This paper analyzes the function of the logic and the implementation adopted in the design of 74181. The understanding of the logic characteristics of this chip enables us to improve future applications.

• Proceedings of the KIEE Conference
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• 2002.11c
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• pp.601-604
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• 2002

In this paper, the timing do-skew modeling for a high speed logic tester channels is developed. The time delay of each channel in a logic tester are different from other channels and it can produce timing error in a test. To get the best timing accuracy in the test with a logic tester, the timing skew must be compensated. The timing skew of channels is due to the difference of time delay of pin-electronics devices composing channels and length of metal line placed on PCB. The expected timing difference of channels can be calculated according to the specifications of pin electronics devices and strip line modeling of PCB. With the calculated delay time, the timing skew compensation circuit has been designed. With the timing skew compensation circuit, the timing calibration of a logic tester can be peformed easily and automatically without other time measuring instruments. The calibration method can then be directly applied to logic testers in mass production lines.

• Progress in Superconductivity and Cryogenics
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• v.4 no.1
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• pp.8-12
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• 2002

Since the high performance analog-to-digital converter can be built with Rapid Single Flux Quantum (RSFQ) logic circuits the development of superconductive analog-to-digital converter has attracted a lot of interests as one of the most prospective area of the application of Josephson Junction technology. One of the main advantages in using Rapid Sng1e Flux Quantum logic in the analog-to-digital converter is the low voltage output from the Josephson junction switching, and hence the high resolution. To design an analog-digital converter, first we have used XIC tool to compose a circuit schematic, and then studied the operational principle of the circuit with WRSPICE tool. Through this process, we obtained the proper circuit diagram of an 1-bit analog-digital converter circuit. The optimized circuit was laid out as a mask drawing. Inductance values of the circuit layout were calculated with L-meter.

• JSTS:Journal of Semiconductor Technology and Science
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• v.10 no.1
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• pp.1-10
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• 2010

This paper proposes a two-phase clocked adiabatic static CMOS logic (2PASCL) circuit that utilizes the principles of adiabatic switching and energy recovery. The low-power 2PASCL circuit uses two complementary split-level sinusoidal power supply clocks whose height is equal to $V_{dd}$. It can be directly derived from static CMOS circuits. By removing the diode from the charging path, higher output amplitude is achieved and the power consumption of the diode is eliminated. 2PASCL has switching activity that is lower than dynamic logic. We also design and simulate NOT, NAND, NOR, and XOR logic gates on the basis of the 2PASCL topology. From the simulation results, we find that 2PASCL 4-inverter chain logic can save up to 79% of dissipated energy as compared to that with a static CMOS logic at transition frequencies of 1 to 100 MHz. The results indicate that 2PASCL technology can be advantageously applied to low power digital devices operated at low frequencies, such as radio-frequency identifications (RFIDs), smart cards, and sensors.

• Proceedings of the KSR Conference
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• 2008.06a
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• pp.1897-1902
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• 2008

The computer system is used in many application domains and any system error in these domains may either cause critical loss or threaten environment or human life. Though examples of these domains can be found in many areas, the system, which is used in domains for carrying passengers including rolling stocks in particular, is expected to show satisfactory operation all the time. The relay control logic, which is used in rolling stocks, is complex in hardware and occupies considerably large volume. Nevertheless, it has been used for a long time, to let the system safely operate even in the occurrence of an error in the computer system. However, the relay control logic circuit is so complex that the analysis of proper circuit operation and interlocking tends to be dependent only on the designer's experiences instead of being systematically performed. Especially, the analysis following a change, addition and deletion of a previous circuit according to the requirements from a source of demand is significantly limited. In this paper, the accuracy of relay control logic is verified by the use of properties of Petri Net model. In addition, how main circuit breaker (MCB) control circuit is modeled and analyzed by the design methodology is shown.

• Journal of the Korea Society of Computer and Information
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• v.3 no.2
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• pp.99-104
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• 1998

In this paper I designed test pattern generator which will be completely detected the faults of multi-stage Logic Circuit. 1 generated this pattern using the test pattern generation Logic Circuit. The generated test patterns compared with the exhausted testing was decreased pattern. This test pattern generator will detect the all single stuck-at faults in the multi-stage Logic Circuit. The choice of which of the many I.C testing methods to use can have a effect on the success or failure of the fault detected. One of the most important considerations is cost and designed test pattern generator is very low cost type.

• Proceedings of the KIEE Conference
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• 2008.07a
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• pp.1957-1958
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• 2008

The Logic Built In Self Test (LBIST) technique is substantially applied in chip design in most many semiconductor company in despite of unavoidable overhead like an increase in dimension and time delay occurred as it used. Currently common LBIST software uses the MISR (Multiple Input Shift Register) However, it has many considerations like defining the X-value (Unknown Value), length and number of Scan Chain, Scan Chain and so on for analysis of result occurred in the process. So, to solve these problems, common LBIST software provides the solution method automated. Nevertheless, these problems haven't been solved automatically by Tri-state Bus in logic circuit yet. This paper studies the simulator and algorithm that judges whether Tri-state Bus lines is the circuit which have X-value or One-hot Value after presuming the control signal of the lines which output X-value in the logic circuit to solve the most serious problems.