• Title/Summary/Keyword: Logic

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Legal and Institutional Outcomes from the 10-year Struggle against Occupational Diseases of Semiconductor workers (반도체 직업병 10년 투쟁의 법·제도적 성과와 과제)

  • Lim, Jawoon
    • Journal of Science and Technology Studies
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    • v.18 no.1
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    • pp.5-62
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    • 2018
  • Over the last 10 years, the fight against occupational diseases of semiconductor workers led by SHARPS(the Supporters for the Health And Rights of People in the Semiconductor industry, NGO) has accomplished considerable achievements, especially in the legal and institutional aspects. First, the court and the government accepted the claims that 24 injured workers respectively filed, recognizing their 10 types of diseases as occupational illness. The court not only expanded the list of work places and diseases that it recognized, but also presented more progressive logic of recognition. The most remarkable achievement among them is the case ruled by the Supreme court in July, 2017. In terms of 'worker's right to know', which is the most important factor in preventing occupational diseases, there have been significant legislative bills, court rulings and government guidelines. The revised bill of the Industrial Safety and Health Act to strengthen workers' rights to know and to introduce the pre-review system on trade secret is currently under review by the National Assembly. The court recently ruled that the government should disclose its inspection results on safety and health management at semiconductor factories. The ministry of labor has drawn up internal guidelines to more actively open its safety and health data to public. This study looks over recent developments in such rulings, bills and guidelines and then, analyzes their implications, laying the groundwork for future actions for worker health in the electronic industry.

A Reconceptualization of Fairness in the Journalism: Focusing on the "Autonomy" (언론 공정성 개념의 재개념화: 언론의 자율성 논변을 중심으로)

  • Moon, Jong-Dae;Yoon, Young-Tae
    • Korean journal of communication and information
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    • v.27
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    • pp.93-122
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    • 2004
  • An examination of the previous works regarding the concept of "fairness" in the journalism revealed that the concept is widely used but remains inadequately defined. Furthermore, there is much less agreement about the characteristics defining "fairness" in the literature. Thus it has often caused disagreement among people who have different political perspectives in the judgment about any media coverage. I suggest a reconceptualization and extension of the construct "fairness" in order to reduce the ambiguity and conflicts in the judgment of fairness among people. Most importantly, drawing on the concept of "autonomy," I attempt to fill in the gap in the model of "fairness." According to the logic of "autonomy," the "fair" press can not exist without the freedom of the press. In other words, all external/internal constraints, which intrude on the freedom of the press, encroach the "fairness" of the press. Thus, the freedom of the press is necessary condition for the fairness in the journalism. However, the freedom of the press is not enough to realize the fairness in the journalism. It needs the sufficient rendition, which is the "autonomy" encompassing the ability of news organization, journalists, and audiences that they resist to any constraints against neutral value. Consequently, the emphasis on the "autonomy" which keeps neutral value perspectives will contribute to reshape the framework for evaluation of "fairness" in journalism.

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An Implementation of Low Power MAC using Improvement of Multiply/Subtract Operation Method and PTL Circuit Design Methodology (승/감산 연산방법의 개선 및 PTL회로설계 기법을 이용한 저전력 MAC의 구현)

  • Sim, Gi-Hak;O, Ik-Gyun;Hong, Sang-Min;Yu, Beom-Seon;Lee, Gi-Yeong;Jo, Tae-Won
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.37 no.4
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    • pp.60-70
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    • 2000
  • An 8$\times$8+20-bit MAC is designed with low power design methodologies at each of the system design levels. At algorithm level, a new method for multipl $y_tract operation is proposed, and it saves the transistor counts over conventional methods in hardware realization. A new Booth selector circuit using NMOS pass-transistor logic is also proposed at circuit level. It is superior to other circuits designed by CMOS in power-delay-product. And at architecture level, we adopted an ELM adder that is known to be the most efficient in power consumption, operating frequency, area and design regularity as the final adder. For registers, dynamic CMOS single-edge triggered flip-flops are used because they need less transistors per bit. To increase the operating frequency 2-stage pipeline architecture is adopted, and fast 4:2 compressors are applied in Wallace tree block. As a simulation result, the designed MAC in 0.6${\mu}{\textrm}{m}$ 1-poly 3-metal CMOS process is operated at 200MHz, 3.3V and consumed 35㎽ of power in multiply operation, and operated at 100MHz consuming 29㎽ in MAC operations, respectively.ly.

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Development of CPLD Technology Mapping Algorithm for Sequential Circuit Improved Run-Time Under Time Constraint (시간제약 조건하에서 순차 회로를 위한 수행시간을 개선한 CPLD 기술 매핑 알고리즘 개발)

  • Yun, Chung-Mo;Kim, Hui-Seok
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.37 no.4
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    • pp.80-89
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    • 2000
  • In this paper, we propose a new CPLD technology mapping algorithm for sequential circuit under time constraints. The algorithm detects feedbacks of sequential circuit, separate each feedback variables into immediate input variable, and represent combinational part into DAG. Also, among the nodes of the DAG, the nodes that the number of outdegree is more than or equal to 2 is not separated, but replicated from the DAG, and reconstructed to fanout-free-tree. To use this construction method is for reason that area is less consumed than the TEMPLA algorithm to implement circuits, and process time is improved rather than TMCPLD within given time constraint. Using time constraint and delay of device the number of partitionable multi-level is defined, the number of OR terms that the initial costs of each nodes is set to and total costs that the$^1$costs is set to after merging nodes is calculated, and the nodes that the number of OR terms of CLBs that construct CPLD is excessed is partitioned and is reconstructed as subgraphs. The nodes in the partitioned subgraphs is merged through collapsing, and the collapsed equations is performed by bin packing so that it fit to the number of OR terms in the CLBs of a given device. In the results of experiments to MCNC circuits for logic synthesis benchmark, we can shows that proposed technology mapping algorithm reduces the number of CLBs by 15.58% rather than the TEMPLA, and reduces process time rather than the TMCPLD.

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An Efficient Dead Pixel Detection Algorithm Implementation for CMOS Image Sensor (CMOS 이미지 센서에서의 효율적인 불량화소 검출을 위한 알고리듬 및 하드웨어 설계)

  • An, Jee-Hoon;Shin, Seung-Gi;Lee, Won-Jae;Kim, Jae-Seok
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.44 no.4
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    • pp.55-62
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    • 2007
  • This paper proposes a defective pixel detection algorithm and its hardware structure for CCD/CMOS image sensor. In previous algorithms, the characteristics of image have not been considered. Also, some algorithms need quite a time to detect defective pixels. In order to make up for those disadvantages, the proposed defective pixel detection method detects defective pixels efficiently by considering the edges in the image and verifies them using several frames while checking scene-changes. Whenever scene-change is occurred, potentially defective pixels are checked and confirmed whether it is defective or not. Test results showed that the correct detection rate in a frame was increased 6% and the defective pixel verification time was decreased 60%. The proposed algorithm was implemented with verilog HDL. The edge indicator in color interpolation block was reused. Total logic gate count was 5.4k using 0.25um CMOS standard cell library.

A CMOS 16:1 Binary-Tree Multiplexer applying Delay Compensation Techniques (딜레이 보상 기법을 적용한 바이너리-트리 구조의 CMOS 16:1 멀티플렉서)

  • Shon, Kwan-Su;Kim, Gil-Su;Kim, Kyu-Young;Kim, Soo-Won
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.45 no.2
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    • pp.21-27
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    • 2008
  • This paper describes a CMOS 16:1 binary-tree multiplexer(MUX) using $0.18-{\mu}m$ technology. To provide immunity for wide frequency range and process-and-temperature variations, the MUX adopts several delay compensation techniques. Simulation results show that the proposed MUX maintains the setup margins and hold margins close to the optimal value, i.e., 0.5UI, in wide frequency-range and in wide process-and-temperature variations, with standard deviation of 0.05UI approximately. These results represent that these proposed delay compensations are effective and the reliability is much improved although CMOS logic circuits are sensitive to those variations. The MUX is fabricated using $0.18-{\mu}m$ CMOS process, and tested with a test board. At power supply voltage of 1.8-V, maximum data-rate and area of the MUX is 1.65-Gb/s and 0.858 $mm^2$, respectively. The MUX dissipates a power of 24.12 mW, and output eye opening is 272.53 mV, 266.55 ps at 1.65-Gb/s operation.

Design of a Readout Circuit of Pulse Rate and Pulse Waveform for a U-Health System Using a Dual-Mode ADC (이중 모드 ADC를 이용한 U-Health 시스템용 맥박수와 맥박파형 검출 회로 설계)

  • Shin, Young-San;Wee, Jae-Kyung;Song, Inchae
    • Journal of the Institute of Electronics and Information Engineers
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    • v.50 no.9
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    • pp.68-73
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    • 2013
  • In this paper, we proposed a readout circuit of pulse waveform and rate for a U-health system to monitor health condition. For long-time operation without replacing or charging a battery, either pulse waveform or pulse rate is selected as the output data of the proposed readout circuit according to health condition of a user. The proposed readout circuit consists of a simple digital logic discriminator and a dual-mode ADC which operates in the ADC mode or in the count mode. Firstly, the readout circuit counts pulse rate for 4 seconds in the count mode using the dual-mode ADC. Health condition is examined after the counted pulse rate is accumulated for 1 minute in the discriminator. If the pulse rate is out of the preset normal range, the dual-mode ADC operates in the ADC mode where pulse waveform is converted into 10-bit digital data with the sampling frequency of 1 kHz. These data are stored in a buffer and transmitted by 620 kbps to an external monitor through a RF transmitter. The data transmission period of the RF transmitter depends on the operation mode. It is generally 1 minute in the normal situation or 1 ms in the emergency situation. The proposed readout circuit was designed with $0.11{\mu}m$ process technology. The chip area is $460{\times}800{\mu}m^2$. According to measurement, the power consumption is $161.8{\mu}W$ in the count mode and $507.3{\mu}W$ in the ADC mode with the operating voltage of 1 V.

The Implementable Functions of the CoreNet of a Multi-Valued Single Neuron Network (단층 코어넷 다단입력 인공신경망회로의 함수에 관한 구현가능 연구)

  • Park, Jong Joon
    • Journal of IKEEE
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    • v.18 no.4
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    • pp.593-602
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    • 2014
  • One of the purposes of an artificial neural netowrk(ANNet) is to implement the largest number of functions as possible with the smallest number of nodes and layers. This paper presents a CoreNet which has a multi-leveled input value and a multi-leveled output value with a 2-layered ANNet, which is the basic structure of an ANNet. I have suggested an equation for calculating the capacity of the CoreNet, which has a p-leveled input and a q-leveled output, as $a_{p,q}={\frac{1}{2}}p(p-1)q^2-{\frac{1}{2}}(p-2)(3p-1)q+(p-1)(p-2)$. I've applied this CoreNet into the simulation model 1(5)-1(6), which has 5 levels of an input and 6 levels of an output with no hidden layers. The simulation result of this model gives, the maximum 219 convergences for the number of implementable functions using the cot(${\sqrt{x}}$) input leveling method. I have also shown that, the 27 functions are implementable by the calculation of weight values(w, ${\theta}$) with the multi-threshold lines in the weight space, which are diverged in the simulation results. Therefore the 246 functions are implementable in the 1(5)-1(6) model, and this coincides with the value from the above eqution $a_{5,6}(=246)$. I also show the implementable function numbering method in the weight space.

Elementary School Students형 Conceptions of Buoyance related with Cognitive Levels (초등학생의 부력 개념 형성과 인지 수준의 관계)

  • 권도현;권성기
    • Journal of Korean Elementary Science Education
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    • v.19 no.1
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    • pp.131-143
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    • 2000
  • The unit of a buoyant force included in the 7th national science curriculum for 6th grade students. On the contrary, it seldom that students' conception about buoyant phenomena is studied, even though there has been many studies of students' conceptions of basic science contents. The purpose of this study was to survey the elementary school students' conceptions of a buoyant force, to analyze their cognitive levels, and to explore the relationships between them. Sixth grade students (total numbers is 192) were selected .from 5 .lasses in two elementary schools in a local city of Kyungsangdo. They were asked to respond two kinds of test, which are the Logical Thinking Ability (GALT) to investigate students' cognitive levels and the Buoyant Force Questionnaire (BFQ). We developed BFQ test, based on the 7th national science curriculum for 6th grade and the previous researches of a buoyant force. We, qualitatively, analysed students' frequency of responses about a buoyant force and their types of explanation, and, quantitatively, analysed the relationships between cognitive levels and conceptions of a buoyant force with SPSS/ PC 7.0 programmes. The results of cognitive level showed that half of 6th grade students were in the concrete operational stage, 43.2% in the transitional stage, 6.8% in the formal stage. However, their sub-logical thinking abilities in a combinational, conservational, controlling variables, proportional, probability and correlational logic were very fluctuated from 91% to 8%. The results that only 4.8% of elementary students had correct conceptions of a buoyant force suggest that 6th grade students had great difficulties in understanding of that concept. Their difficulties would originated from the frequent common-sense explanations of a buoyant phenomena in terms of the weight or the unique properties or the contact area of an object or with/without air. Furthermore students' explanations, frequently, changed with context of problems of a buoyant force. Scheffe test of quantitative results that elementary students in the concrete level had 50.6% of concept formation in a buoyant force, the transitional level 54.5%, and in the formal operational level 62.8% showed significant differences of conceptions of a buoyant force with cognitive levels. Therefore the concrete operational elementary students had more difficulties of understanding of a buoyant force than the transitional and formal level, which is required to higher cognitive levels. This conclusion have implications that the unit of a buoyant force have to be presented with concrete activities for majority of students who are in concrete and transitional levels.

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An Exploratory Study on 'school violence prevention' in Home Economics Education (학교폭력 예방을 위한 가정과교육의 접근 방안 탐색)

  • Wang, SeokSoon
    • Journal of Korean Home Economics Education Association
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    • v.25 no.1
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    • pp.119-135
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    • 2013
  • This Exploratory study applied the content analysis method by documental research to develop the logic of announcing a validity of Korean Education or Home Economics Education's roles and missions for preventing the school violence. As the results, three logics of accessing devices for Korean Education or Home Economics Education got developed. First, adolescents should be changed into an positive perspective like a 'people living' rather than a negative perspective like the 'learner' which is limited in Korean Education. Second, the value of the 'life competency' which has been disparaging is reinforced as an important value of education although the purpose of Korean Education was only one. The life competency is not a talent which is learned naturally by experiences. Because the school violence which is a problem in nowadays is a problem occurred by adolescents as the 'people living' rather than the 'learner', it is needed to renovate an education by a curriculum of reinforcing the 'life competency'. Third, Home Economics Education has been traditionally the typical subject which had a purpose of varied competency development as the 'people living'. Thus, the subject of Home Economics Education is one of the most important subjects, being able to prevent the school violence in entire Korean Education. The Home Economics Education as the 'life education' has an essence for making adolescents have needed competency to achieve a qualified and happy life over their adjustment.

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