• 대한임베디드공학회논문지
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• 제15권5호
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• pp.235-242
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• 2020

This paper analyzes the effect of reduced output width of the truncated logarithmic multiplication and application to inferences using convolutional neural networks (CNNs). For small hardware overhead, output width is reduced in the truncated Mitchell multiplier, so that fractional bits in multiplication output are minimized in error-resilient applications. This analysis shows that when reducing output width in the truncated Mitchell multiplier, even though worst-case relative error increases, average relative error can be kept small. When adopting 8 fractional bits in multiplication output in the evaluations, there is no significant performance degradation in target CNNs compared to existing exact and original Mitchell multipliers.

• KSII Transactions on Internet and Information Systems (TIIS)
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• 제13권11호
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• pp.5616-5630
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• 2019

Fully homomorphic encryption allows a third-party to perform arbitrary computation over encrypted data and is especially suitable for secure outsourced computation. This paper investigates secure outsourced computation of multiple matrix multiplication based on fully homomorphic encryption. Our work significantly improves the latest Mishra et al.'s work. We improve Mishra et al.'s matrix encoding method by introducing a column-order matrix encoding method which requires smaller parameter. This enables us to develop a binary multiplication method for multiple matrix multiplication, which multiplies pairwise two adjacent matrices in the tree structure instead of Mishra et al.'s sequential matrix multiplication from left to right. The binary multiplication method results in a logarithmic-depth circuit, thus is much more efficient than the sequential matrix multiplication method with linear-depth circuit. Experimental results show that for the product of ten 32×32 (64×64) square matrices our method takes only several thousand seconds while Mishra et al.'s method will take about tens of thousands of years which is astonishingly impractical. In addition, we further generalize our result from square matrix to non-square matrix. Experimental results show that the binary multiplication method and the classical dynamic programming method have a similar performance for ten non-square matrices multiplication.

• ETRI Journal
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• 제43권4호
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• pp.684-693
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• 2021

This paper presents a low-cost two-stage approximate multiplier for bfloat16 (brain floating-point) data processing. For cost-efficient approximate multiplication, the first stage implements Mitchell's algorithm that performs the approximate multiplication using only two adders. The second stage adopts the exact multiplication to compensate for the error from the first stage by multiplying error terms and adding its truncated result to the final output. In our design, the low-cost multiplications in both stages can reduce hardware costs significantly and provide low relative errors by compensating for the error from the first stage. We apply our approximate multiplier to the convolutional neural network (CNN) inferences, which shows small accuracy drops with well-known pre-trained models for the ImageNet database. Therefore, our design allows low-cost CNN inference systems with high test accuracy.

• 대한수학회보
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• 제51권4호
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• pp.1101-1113
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• 2014

We give analogous criterion to admit a real parabolic connection on real parabolic bundles over a real curve. As an application of this criterion, if real curve has a real point, then we proved that a real vector bundle E of rank r and degree d with gcd(r, d) = 1 is real indecomposable if and only if it admits a real logarithmic connection singular exactly over one point with residue given as multiplication by $-\frac{d}{r}$. We also give an equivalent condition for real indecomposable vector bundle in the case when real curve has no real points.

• 대한기계학회논문집A
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• 제25권11호
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• pp.1887-1894
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• 2001

The effects of carbon black on the material properties and the fatigue life of the carbon-black filled natural rubbers were investigated. Different kinds of carbon blacks resulted in different fatigue lives, hysteresis, and critical J-values. It was noticed that the hysteresis was inversely proportional to the difference between DBPA and CTAB, and the critical J-value was almost the same regardless of the length of a precrack. In addition, different kinds of carbon blacks resulted in different fracture morphologies, and micro-scale and macro-scale roughnesses. The critical J-value was proportional to the micro-scale roughness. and it seemed relate to the size distribution of carbon black particles. By reviewing all the experimental data. it was finally noticed that the logarithmic value of the fatigue life could be linearly expressed by a multiplication of the critical J-value and the logarithmic value of the hysteresis.

• 한국정보통신학회:학술대회논문집
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• 한국해양정보통신학회 2010년도 춘계학술대회
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• pp.809-811
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• 2010

3차원 그래픽 응용이 가능한 소형 모바일 기기에서의 부동소수점 연산 처리는 전력소모가 많고 하드웨어 비용이 많이 들며 연산 해상도가 너무 정확한 연산보다는 적절한 해상도를 확보하되 하드웨어 자원을 적게 소모하고 전력소모가 낮을수록 바람직하다. 비용이 많이 소요되는 부동소수점 연산은 곱셈과 나눗셈이며, 로그 변환을 이용하면 곱셈과 나눗셈을 덧셈과 뺄셈으로 변환하여 고속 동작을 구현할 수 있으며, 이는 로그 함수값을 얼마나 실제값에 근사화 시킬 수 있는지에 따라 성능이 좌우된다. 본 연구에서는 이러한 고속 부동소수점 연산에 적용될 수 있는 로그변환 회로에 대한 동향을 조사하되, 설계 시 중요하게 고려해야 할 점과 로그변환 회로가 어떻게 근사화되고 적용될 수 있는지에 대하여 상세히 분석한다.

• 융합신호처리학회논문지
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• 제10권4호
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• pp.289-293
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• 2009

This study proposes a novel double-base log encoder (DBLE) for flash Analog-to-Digital converters (ADCs). Analog inputs of flash ADCs are represented in logarithmic number systems with bases of 2 and 3 at the outputs of DBLE. A look up table stores the sets of exponents of base 2 and 3 values. This algorithm improves the performance of a DSP (Digital Signal Processor) system that takes outputs of a flash ADC, since the double-base log number representation does multiplication operation easily within negligible error range in ADC. We have designed and implemented 6 bits DBLE implemented with ROM (Read-Only Memory) architecture in a $0.18\;{\mu}m$ CMOS technology. The power consumption and speed of DBLE are better than the FAT tree and binary ROM encoders at the cost of more chip area. The DBLE can be implemented into SoC architecture with DSP to improve the processing speed.