• IEMEK Journal of Embedded Systems and Applications
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• v.15 no.5
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• pp.235-242
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• 2020

This paper analyzes the effect of reduced output width of the truncated logarithmic multiplication and application to inferences using convolutional neural networks (CNNs). For small hardware overhead, output width is reduced in the truncated Mitchell multiplier, so that fractional bits in multiplication output are minimized in error-resilient applications. This analysis shows that when reducing output width in the truncated Mitchell multiplier, even though worst-case relative error increases, average relative error can be kept small. When adopting 8 fractional bits in multiplication output in the evaluations, there is no significant performance degradation in target CNNs compared to existing exact and original Mitchell multipliers.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.13 no.11
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• pp.5616-5630
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• 2019

Fully homomorphic encryption allows a third-party to perform arbitrary computation over encrypted data and is especially suitable for secure outsourced computation. This paper investigates secure outsourced computation of multiple matrix multiplication based on fully homomorphic encryption. Our work significantly improves the latest Mishra et al.'s work. We improve Mishra et al.'s matrix encoding method by introducing a column-order matrix encoding method which requires smaller parameter. This enables us to develop a binary multiplication method for multiple matrix multiplication, which multiplies pairwise two adjacent matrices in the tree structure instead of Mishra et al.'s sequential matrix multiplication from left to right. The binary multiplication method results in a logarithmic-depth circuit, thus is much more efficient than the sequential matrix multiplication method with linear-depth circuit. Experimental results show that for the product of ten 32×32 (64×64) square matrices our method takes only several thousand seconds while Mishra et al.'s method will take about tens of thousands of years which is astonishingly impractical. In addition, we further generalize our result from square matrix to non-square matrix. Experimental results show that the binary multiplication method and the classical dynamic programming method have a similar performance for ten non-square matrices multiplication.

• ETRI Journal
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• v.43 no.4
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• pp.684-693
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• 2021

This paper presents a low-cost two-stage approximate multiplier for bfloat16 (brain floating-point) data processing. For cost-efficient approximate multiplication, the first stage implements Mitchell's algorithm that performs the approximate multiplication using only two adders. The second stage adopts the exact multiplication to compensate for the error from the first stage by multiplying error terms and adding its truncated result to the final output. In our design, the low-cost multiplications in both stages can reduce hardware costs significantly and provide low relative errors by compensating for the error from the first stage. We apply our approximate multiplier to the convolutional neural network (CNN) inferences, which shows small accuracy drops with well-known pre-trained models for the ImageNet database. Therefore, our design allows low-cost CNN inference systems with high test accuracy.

• Bulletin of the Korean Mathematical Society
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• v.51 no.4
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• pp.1101-1113
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• 2014

We give analogous criterion to admit a real parabolic connection on real parabolic bundles over a real curve. As an application of this criterion, if real curve has a real point, then we proved that a real vector bundle E of rank r and degree d with gcd(r, d) = 1 is real indecomposable if and only if it admits a real logarithmic connection singular exactly over one point with residue given as multiplication by $-\frac{d}{r}$. We also give an equivalent condition for real indecomposable vector bundle in the case when real curve has no real points.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.25 no.11
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• pp.1887-1894
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• 2001

The effects of carbon black on the material properties and the fatigue life of the carbon-black filled natural rubbers were investigated. Different kinds of carbon blacks resulted in different fatigue lives, hysteresis, and critical J-values. It was noticed that the hysteresis was inversely proportional to the difference between DBPA and CTAB, and the critical J-value was almost the same regardless of the length of a precrack. In addition, different kinds of carbon blacks resulted in different fracture morphologies, and micro-scale and macro-scale roughnesses. The critical J-value was proportional to the micro-scale roughness. and it seemed relate to the size distribution of carbon black particles. By reviewing all the experimental data. it was finally noticed that the logarithmic value of the fatigue life could be linearly expressed by a multiplication of the critical J-value and the logarithmic value of the hysteresis.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2010.05a
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• pp.809-811
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• 2010

In most floating-point operations related with 3D graphic applications for mobile devices, properly approximated data calculations with reduced complexity and low power are preferable to exactly rounded floating-point operations with unnecessary preciseness with cost. Among all the sophisticated floating-point arithmetic operations, multiplication and division are the most complicated and time-consuming, and they can be transformed into addition and subtraction repectively by adopting the logarithmic conversion. In this process, the most important factor for performance is how high we can make an approximation of the logarithm conversion. In this paper, we cover the trends in studying the logarithm conversion circuit designs. We also discuss the important factor in design issues and the applicable fields in detail.

• Journal of the Institute of Convergence Signal Processing
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• v.10 no.4
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• pp.289-293
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• 2009

This study proposes a novel double-base log encoder (DBLE) for flash Analog-to-Digital converters (ADCs). Analog inputs of flash ADCs are represented in logarithmic number systems with bases of 2 and 3 at the outputs of DBLE. A look up table stores the sets of exponents of base 2 and 3 values. This algorithm improves the performance of a DSP (Digital Signal Processor) system that takes outputs of a flash ADC, since the double-base log number representation does multiplication operation easily within negligible error range in ADC. We have designed and implemented 6 bits DBLE implemented with ROM (Read-Only Memory) architecture in a $0.18\;{\mu}m$ CMOS technology. The power consumption and speed of DBLE are better than the FAT tree and binary ROM encoders at the cost of more chip area. The DBLE can be implemented into SoC architecture with DSP to improve the processing speed.