• Journal of Energy Engineering
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• v.15 no.1 s.45
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• pp.23-27
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• 2006

This paper presents the evaluation of LPG (Liquefied petroleum gas) regulators for home use. For the evaluation, several properties of the regulators were experimentally analyzed, such as the operation of safety device, the adjusting and lock-up pressure, the adjusting spring and the diaphragm, with respect to the used time of the regulators. Experimental results showed that the initial operation performance of regulators were degraded with increase of the service time and also showed that the degradation of the performance and material property could become serious after six-year-use of the regulator.

• The Journal of the Acoustical Society of Korea
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• v.13 no.6
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• pp.24-30
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• 1994

In this paper, the system for detection of photoacoustic signal has been constructed by using CW $CO_{2}$ laser for an analysis of the photoacoustic signal In metals and aluminum carbon steel, brass have been used as sample. The photoacoustic signals of several nano amperes have been detected in each sample with varying modulation frequency of laser, time constant of lock-in amplifier, thickness of sample. The characteristics of photoacoustic signal has been analysed in term of phase angle by using signal processing technique. Results indicate that the photoacoustic signal can be stabilized by adjustment of time constant of lock-in amplifier, that the signal amplitude is proportional to the ratio of thermal expansion coefficient to thermal capacity of metal, and that the signal amplitude decreases exponentially with sample thickness as well as with modulation frequency.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.48 no.12
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• pp.28-34
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• 2011

In this paper, a PLL frequency synthesizer for RSSI applications is designed by phase noise analysis. Required synthesizer performance is achieved by optimizing the noise performance of PLL components and a loop transfer function, since its phase noise, lock time, and spur suppression capability are determined by the performance of loop components and loop filter characteristics. As an application example, a PLL frequency synthesizer for RSSI applications, which operates at the frequency of 2.288GHz, is designed using the phase noise analysis. The validity of the design technique is proved by experiments.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.10 no.4
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• pp.1751-1767
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• 2016

Home security has become the prime concern for everyone in present scenario. In this work an attempt has been made to develop a home security system which is accessible, affordable and yet effective.The proposed system is based on 'Remote Embedded Control System' (RECS) which works both on the web and gsm platform for authentication and monitoring. This system is therefore cost effective as it relies on existing network infrastructure. As PCA is most popular and efficient algorithm for face recognition, it has been usedin this work. Next to it an interface has been developed for communication purpose in the embedded security system through the ZigBee module. Based on this embedded system, automated control of door movement has been implemented through electromagnetic door lock technology. This helps the users to monitor the real-time activities through web services/SMS. The web service consists of either web browser command or e-mail provision. The system establishes the communication between the system and authenticated user. The e-mail received by the system from the authorized person will monitor and control the real-time operation and door lock. The entire control system is reinforced using ARM1176JZF-S microcontroller and tested for actual use in the home environment. The result shows the experimental verification of the proposed system.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.22 no.2
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• pp.258-264
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• 2011

In this paper, we designed a frequency synthesizer with a low phase noise and fast lock time and excellent spurious characteristics using the offset-PLL(Phase Locked Loop) that is used in GSM(Global System for Mobile communications). The proposed frequency synthesizer has low phase noise using three times down conversion and third offset frequency of this synthesizer is created by DDS(Direct Digital Synthesizer) to have high frequency resolution. Also, this synthesizer has fast switching speed using DAC(Digital to Analog Converter). but phase noise degraded due to DAC. we improved performance using the DAC noise filter.

• ETRI Journal
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• v.28 no.4
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• pp.435-443
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• 2006

This paper presents an efficient carrier recovery algorithm combined with a turbo-coding technique in a mobile communication system. By using a block turbo code made up of independently decodable block codes, we can efficiently recover the fast time-varying carrier phase as well as correct channel errors. Our simulation results reveal that the proposed scheme can accommodate mobiles with high speed, and at the same time can reduce the number of iterations to lock the phase.

• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.83-86
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• 2000

This paper describes a delay-locked loop(DLL_) with low-jitter using Vernier Method. This DLL can be used to synchronize the internal clock to the external clock with very short time interval and fast lock-on. The proposed circuit was simulated in a 0.25 $\mu\textrm{m}$ CMOS technology to realize low-jitter. We verified 50-ps of time interval within 5 clock cycles of the clock as the simulation results.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.18 no.4 s.119
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• pp.423-429
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• 2007

The clock recovery module of gap filler for satellite DMB is proposed. Proposed module sustains the output frequency of 10 MHz whether the received signal from the satellite is unstable or cut off within 0.5 sec. The advantages of this module is without frequency tuning at regular interval and low material cost. This module is fabricated by using CPLD as clock recovery IC and new type of loop filter for satisfying the fast lock time and long hold over time simultaneously. The measured performance of the fabricated module has a holdover time of 11 sec at frequency stability less than 0.01 ppm, and phase noise of -113 dBc/Hz at 100 Hz offset.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.10
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• pp.87-95
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• 2014

This paper describes a dual channel receiver design for CIS interfaces. Each channel includes CTLE(Continuous Time Linear Equalizer), sampler, deserializer and clocking circuit. The clocking circuit is composed of PLL, PI and CDR. Fast lock acquisition time, short latency and better jitter tolerance are achieved by adding OSPD(Over Sampling Phase Detector) and FSM(Finite State Machine) to PI-based CDR. The CTLE removes ISI caused by channel with -6 dB attenuation and the lock acquisition time of the CDR is below 1 baud period in frequency offset under 8000ppm. The voltage margin is 368 mV and the timing margin is 0.93 UI in eye diagram using 65 nm CMOS technology.

• Journal of the Korean Society of Costume
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• v.53 no.7
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• pp.139-146
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• 2003

This study was aimed at analyzing a characteristics of the sewing machines and analyzing the effective sewing time in the garment manufacture process, therefore to obtain the basic data concerned with the sewing. operation standardization. The two methods were experimented. First, two garment factories established in Seoul and Geonggi province were randomly selected for the analyzing the sewing speed of the sewing operator for the optimized sewing speed using the equipment of Digital Tachometer HT4100. Second, five garment factories established in Seoul and Geonggi province were randomly selected to analyze the required time data to reach the fixed sewing speed using the lock stitch sewing machine which was used in the sewing factories. The results are divided into 3 categories as follows; 1) Survey results for the optimized sewing speed : The sewing operations of 10~20 cm range were most frequently selected in seam constructions in Korean sewing factories, and the sewing speed of 2,500 R.P.M was most used; 2) Required time to reach the fixed sewing speed using the lock stitch sewing machine : The mean of required time to the fixed sewing speed of 2.500 R.P.M was 3.5 second, and the mean of the real-sewing length during the 3.5 second was 43.8 cm ; 3) Analysis of the optimized sewing speed calculated using these results : The optimized sewing speed for the sewing manufacturers of the upward of 43.8 cm was 2,500 R.P.M. and for the sewing manufacturers of the below of 42.2 cm, the optimized sewing speed was 2.450 R.P.M.