• 한국방재학회:학술대회논문집
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• 2008.02a
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• pp.233-236
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• 2008

To analyze the saline intrusion in the place, such as an estuary, the three-dimensional numerical model is developed. In this study, the advection terms of the governing equations are discretized by upwind scheme. By using an explicit scheme for the longitudinal direction and an implicit scheme for the vertical direction, the numerical model is free from the restriction of temporal step size caused by a relatively small grid ratio. The equation of state is used to consider the density, and the scalar transport equation for salinity is employed the third order TVD to scheme to prevent unphysical oscillation near discontinuity. In order to verify saline intrusion, the numerical model is conducted to compare the previous model in the lock exchange. The present model generally show a good agreement with the previous one.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.51 no.4
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• pp.144-151
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• 2002

This paper presents a fault-tolerant duplex architecture to build a high-reliability microcontroller using commercial VLSI processors. The architecture supports fail-silence under all single-failure situations and facilitates recovery from transient failures. The paper implements the duplex architecture using two Motorola MC68360 processors and evaluates its fault tolerance in a real application environment.

• The Journal of the Korea institute of electronic communication sciences
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• v.4 no.4
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• pp.247-252
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• 2009

This paper presents an Integer-N phase-locked loop (PLL) frequency synthesizer using a novel prescaler based on a charge pump and clock triggering circuit. A quadrature VCO has been designed for the 900MHz UHF RFID application. In this circuit, a voltage-controlled oscillator(VCO), a novel Prescaler, phase frequency detector(PFD), charge pump(CP), and analog lock detector(ALD) have been integrated with 0.35-${\mu}m$CMOS process. The integer divider has been developed with a verilog-HDL module, and the PLL mixed mode simulation has been performed with Spectre-Verilog co-simulator. The sweep range of VCO is designed from 828 to 960 MHz and the VCO generates four phase quadrature signals. The simulation results show that the phase noise of VCO is -102dBc/Hz at 100 KHz offset frequency, and the maximum lock-in time is about 4us with 32MHz step change (from 896 to 928 MHz).

• Journal of the Korean Institute of Telematics and Electronics
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• v.20 no.4
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• pp.55-60
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• 1983

A new type of digital phase-locked loop (DPLL) that employs a multilevel quantified timing error detector (TED) is proposed and analyzed under the assumption of negligible quantizing effect and no noise. Since the timing error is quantized uniformly, the TED has a linear characteristic. From the linear characteristic of TED, a first order difference equation describing the behavior of the loop is derived. Using the system equation, the loop is analyzed mathematically for phase step and frequency step input. Desired locking condition for the loop to be locked and the lock range for the DPLL's to achieve exact locking independently of initial conditions are ob-tained. And these analyses are confirmed by timing error plane plots and computer simulation.

• Bulletin of the Korean Chemical Society
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• v.35 no.3
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• pp.743-748
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• 2014

In this work, we describe a very simple electroless deposition method to prepare moderate-SERS-active nanostructured Pd films deposited on the glass substrates. To the best of our knowledge, this is the first report on the one-pot electroless method to deposit Pd nanostructures on the glass substrates. This method only requires the incubation of negatively charged glass substrates in ethanol-water mixture solutions of $Pd(NO_3)_2$ and butylamine at elevated temperatures. Pd films are then formed exclusively and evenly on glass substrates. Due to the aggregated structures of Pd, the SERS spectra of benzenethiol and organic isonitrile could be clearly identified using the Pd-coated glass as a SERS substrate. This one-step fabrication method of Pd thin film on glass is cost-effective and suitable for the mass production.

• Journal of the Korean institute of surface engineering
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• v.24 no.4
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• pp.215-221
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• 1991

Microstructure evolution during low temperature vapor deposition exhibits wel-developed columnar structure mainly owing to geometrical shadowing effect of surface roughness. It is concluded that this structure is concided with many theoretical models suggested so far. In case of aluminum nitride film deposition consisted of etching and nitriding step employing ECR plasma, the rougher the surface before etching, the finer and more cone-and-whisker structure can be developed. In turn, this fine structure affects the formation and growth of columnar as well as offers many sites available for mechanical lock-up. Conclusively, the formation of well-defined columnar structures depends on the initial surface roughness.

• Korean Journal of Computational Design and Engineering
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• v.14 no.4
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• pp.225-233
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• 2009

The objective of this paper is to examine a construction method and verify PLC logic using the logical modeling and simulation of a virtual plant has complex manufacturing system and the domain of application is car body assembly line of automotive industrial operated by PLC Program. The proposed virtual plant model for the analysis of the construction method consists of three types of components which are virtual device, intermediary transfer and controller is modeled by logical model but it the case of the verification of PLC program, HMI and PLC logic in the field substitute for the controller. The implementation of the proposed virtual plant model is conducted PLC Studio which is an object-oriented modeling language based on logical model. As a result, proposed methods enable 3D graphics is designed in the analysis step to use for verification of PLC program without special efforts.

• 연구논문집
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• s.31
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• pp.89-99
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• 2001

This paper presents the modeling and analysis of dynamic characteristics of hydraulic snubber in electric power plant. The nonlinear state-space model of 14th order to describe the dynamics of the snubber was established by Simulink. The simulation results show that the hydraulic snubber reacts as like the conventional shock absolvers against the high pulse shock load. The snubber also shows the peculiar characteristics to the small step load, which temporarily lock the control valves up, however maintain same steady-state pressures of all internal chambers in the long run. Two case studies for the analysis of the snubber are addressed. Practical pulse testing method was also proposed to identify the frequency response of the snubber.

• Journal of the Korea Society of Computer and Information
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• v.20 no.3
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• pp.9-17
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• 2015

The ISO 26262 standard requires a preliminary hazard analysis and risk assesment early in the development for automotive system. This is a first step for the development of an automotive system to determine the necessary safety measures to be implemented for a certain function. In this paper, we propose an ontology-based hazard analysis and risk assessment method for automotive functional safety. We use ontology to model the hazard and SWRL(Semantic Web Language) to describe risk analysis. The applicability of the proposed method is evaluated by the case study of an ESCL(electronic steering column lock) system. The result show that ontology deduction is useful for improving consistency and accuracy of hazard analysis and risk assessment.

• Journal of the Korean Society of Industry Convergence
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• v.21 no.6
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• pp.265-271
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• 2018

DC-DC buck converter is a critical building block in the power management integrated circuit (PMIC) architecture for the portable devices such as cellular phone, personal digital assistance (PDA) because of its power efficiency over a wide range of conversion ratio. To ensure a safe operation, avoid unexpected damages and enhance the reliability of the converter, fully-integrated protection circuits such as over voltage protection (OVP), under voltage lock out (UVLO), startup, and thermal shutdown (TSD) blocks are designed. In this paper, these three fully-integrated protection circuit blocks are proposed for use in the DC-DC buck converter. The buck converter with proposed protection blocks is operated with a switching frequency of 1 MHz in continuous conduction mode (CCM). In order to verify the proposed scheme, the buck converter has been designed using a 180 nm CMOS technology. The UVLO circuit is designed to track the input voltage and turns on/off the buck converter when the input voltage is higher/lower than 2.6 V, respectively. The OVP circuit blocks the buck converter's operation when the input voltage is over 3.3 V, thereby preventing the destruction of the devices inside the controller IC. The TSD circuit shuts down the converter's operation when the temperature is over $85^{\circ}C$. In order to verify the proposed scheme, these protection circuits were firstly verified through the simulation in SPICE. The proposed protection circuits were then fabricated and the measured results showed a good matching with the simulation results.