• Proceedings of the KIEE Conference
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• 1999.07c
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• pp.1287-1289
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• 1999

The UPFC(Unified Power Flow Controller) controls the magnitude and phase of the series injected voltage to exchange the real and reactive power with transmission line. The UPFC consists of two inverters connected together through the DC link capacitor. This paper describes the detailed UPFC switching-level model. PWM (Pulse Width Modulation) method is chosen to operate the inverters. Automatic voltage control mode and automatic power flow control mode is selected to control the UPFC. EMTP simulation is offered to obtain the basic operation characteristics of the UPFC and the dynamic characteristics of the UPFC is studied in detail.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.9 no.11
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• pp.4419-4435
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• 2015

The use of an efficient packet scheduling scheme for a forward link in satellite communication networks is very important to support fairness for each return channel satellite terminal (RCST) and the service differentiations for user traffics. To support fairness and QoS for each RCST with service-level agreement (SLA), the Adaptive Coding and Modulation (ACM) system in a satellite hub has to process packets with considering modulation and coding (MODCOD) and packet types. Although a DVB-S2 system with ACM scheme has higher transmission efficiency, it cannot offer fairness or quality of service (QoS) to RCSTs. Because the data are transmitted with high MODCOD in regions with clear skies, while data are transmitted using low MODCOD in regions experiencing rain events. In this paper, we propose a two-step scheduling scheme offering fairness and QoS to RCSTs, while minimizing a decrease in throughput. The proposed scheme is carried out performance evaluations using a computer simulation. As results of this simulation, the proposed scheduler was shown to support bandwidth fairness to an individual RCST, and provide a level of QoS differentiation for user traffics.

• Journal of Power Electronics
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• v.18 no.6
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• pp.1819-1829
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• 2018

A three-phase, three-switch, and three-level boost-type PWM rectifier (Vienna rectifier) is proposed as an active front-end power factor correction (PFC) rectifier for telecom loads. The proposed active front-end PFC rectifier system is modeled by the switching cycle average model. The relation between duty ratios and DC link capacitor voltages is derived in terms of the system input currents. Furthermore, the feasible switching states are identified and applied to the proposed system to reduce the switching stress and DC ripples. A detailed equivalent circuit analysis of the proposed front-end PFC rectifier is conducted, and its performance is verified through simulations in MATLAB. Simulation results are verified using an experimental setup of an active front-end PFC rectifier that was developed in the laboratory. Simulation and experimental results demonstrate the improved power quality parameters that are in accordance with the IEEE and IEC standards.

• The Transactions of the Korean Institute of Power Electronics
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• v.25 no.4
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• pp.319-328
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• 2020

The recent use of distributed power generation systems constructed with DC-DC converters has become extremely popular owing to the rising need for environment friendly energy generation power systems. In this study, a new single-phase five-level inverter for off-grid applications constructed with a multilevel DC-DC step-up converter is proposed to boost a low-level DC voltage (36 V-64 V) to a high-level DC bus (380 V) and invert and connect them with a single-phase 230 V rms AC load. Compared with other traditional multilevel inverters, the proposed five-level inverter has a reduced number of switching devices, can generate high-quality power with lower THD values, and has balanced voltage stress for DC capacitors. Moreover, the proposed topology does not require multiple DC sources. Finally, the performance of the proposed topology is presented through the simulation and experimental results of a 400 W hardware prototype.

• Journal of Power Electronics
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• v.16 no.2
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• pp.455-463
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• 2016

This paper proposes a compensation method to improve the distorted space vectors when a 3-level Neutral Point Clamped (NPC) inverter has an unbalanced neutral point voltage. Since both the neutral point voltage of the DC link and the space vector of a 3-level NPC inverter are closely related depending on the output load connecting state, a distorted space vector can occur when the neutral point voltage of a 3-level NPC inverter is unbalanced. The proposed method can improve the distorted space vectors by adjusting the injection time of the small and medium vectors and by modulating the amplitude of the carrier waveforms. In this paper, the proposed method is verified by both simulation and experimental results based on a 3-level NPC inverter.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.12B
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• pp.1017-1027
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• 2006

Recently, Internet service providers are offering triple play service which combines voice and video services with the existing high speed Internet service under the common network infrastructure of IP protocol, so that they can create more benefit from operating a single network architecture. In line with this movement in the convergence of network and services, in this work we propose a bandwidth dimensioning method for the subscriber network of the IP network at flow level. To that purpose, let us propose a series of bandwidth dimensioning methods: bandwidth for best effort service only, bandwidth dimensioning for premium services, and bandwidth dimensioning schemes for the premium Internet services as well as the best effort service which comprise the TPS. Our link dimensioning method is based on the flow level that incorporates the flow blocking probability as a measure of grade of services(GoS), and investigates the characteristics of the proposed methods via extensive numerical experiments. After that, let us carry out a simulation experiment concerning the delay and loss performance of the packet scheduling for the premium services (QoS) using the bandwidth designed by our proposed method, via which the packet level quality of service (QoS) for the proposed link dimensioning method can be observed.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.1
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• pp.47-52
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• 2004

This paper presents a CMOS optical receiver design featuring wide input dynamic range and low bit error rate suitable for FTTH application. We achieved 60dB input dynamic range for up to 100Mbps by controlling the PMOS feedback resistance of transimpedance preamplifier according to its output signal level. Auto-bias circuit is designed in current mirror configuration to minimize duty error. Circuit simulation has been performed using 2-poly, 3-metal, 0.6um CMOS process parameters. The designed receiver consumes less than 130mW at 100Mbps with 5V power supply.

• The KIPS Transactions:PartC
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• v.18C no.6
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• pp.441-444
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• 2011

In this study, we present a method for efficiently aggregating network state information. It is especially useful for aggregating links that have both delay and bandwidth in an asymmetric network. Proposed method reduces the information distortion of logical link by integration process after similar measure and grouping of logical links in multi-level topology transformation to reduce the space complexity. It is applied to transform the full mesh topology whose Service Boundary Line (SBL) serves as its logical link into a spanning tree topology. Simulation results show that aggregated information accuracy and query response accuracy are higher than that of other known method.

• Journal of Electrical Engineering and Technology
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• v.12 no.5
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• pp.1872-1882
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• 2017

Medium voltage drive systems driven by high-power multi-level inverters operating at low switching frequency can reduce the switching losses of the power device and increase the output power. Employing subsection synchronous current harmonic minimum pulse width modulation (CHMPWM) technique can maintain the total harmonic distortion of current at a very low level. It can also reduce the losses of the system, improve the system control performance and increase the efficiency of DC-link voltage accordingly. This paper proposes a subsection synchronous CHMPWM approach of active neutral point clamped five-level (ANPC-5L) inverter under low switching frequency operation. The subsection synchronous scheme is obtained by theoretical calculation based on the allowed maximum switching frequency. The genetic algorithm (GA) is adopted to get the high-precision initial values. So the expected switching angles can be achieved with the help of sequential quadratic programming (SQP) algorithm. The selection principle of multiple sets of the switching angles is also presented. Finally, the validity of the theoretical analysis and the superiority of the CHMPWM are verified through both the simulation results and experimental results.

• Proceedings of the KIEE Conference
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• 1998.07f
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• pp.1905-1907
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• 1998

The multi-level approach seems to be best suited to high power, high voltage ac drives with low torque ripple and fast dynamic response. If high control performance is required, space vector control becomes desirable, and the task becomes time critical. In this paper, a simplified space vector PWM method for the control of a three level inverter is proposed. As the PWM is simple in structure, it is easy to implement and the fluctuation of the neutral point potential of DC link can be supressed effectively. The simulation results demonstrate that the proposed PWM strategy can be applied to high power, high voltage inverter systems. And its application to multi-level inverter is easily done on the same principle.