• 전자공학회논문지S
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• 제34S권8호
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• pp.45-55
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• 1997

To design a ATM Switch which ahs advantages in high sped packet switching, it is essential to set multiple paths between input ports and output ports and to design a new packet transfer technique on that paths for decreasing Packet Loss by conflicts in internal Switch Plane. We propose new packet transfer method, Alternate Path Transfer Mechanism by Dynamic Bypass Transfer Method which can solve conflict problem in Banyan network easily. Proposed ATM Switch consists of Banyan networks, Input/Ouput Port, Bypass Link, and Bypass Link Controller. Packets caused conflicts in SEs have another chances of packet transfer over alternate switching planes by using this mechanism.

• Journal of Power Electronics
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• 제3권4호
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• pp.249-258
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• 2003

This paper presents a high-efficient and cost effective three-phase AC/DC-DC/AC power conversion system with a single two-switch type active Auxiliary Resonant DC Link (ARDCL) snubber circuit, which can minimize the total power dissipation. The active ARDCL snubber circuit is proposed in this paper and its unique features are described. Its operation principle in steady-state is discussed for the three phase AC/DC-DC/AC converter, which is composed of PWM rectifier as power factor correction (PFC) converter, sinewave PWM inverter. In the presented power converter system not only three-phase AC/DC PWM rectifier but also three-phase DC/AC inverter can achieve the stable ZVS commutation for all the power semiconductor devices. It is proved that the proposed three-phase AC/DC-DC/AC converter system is more effective and acceptable than the previous from the cost viewpoint and high efficient consideration. In addition, the proposed two-switch type active auxiliary ARDCL snubber circuit can reduce the peak value of the resonant inductor injection current in order to maximize total system actual efficiency by using the improved DSP based control scheme. Moreover the proposed active auxiliary two-switch ARDCL snubber circuit has the merit so that there is no need to use any sensing devices to detect the voltage and current in the ARDCL sunbber circuit for realizing soft-switching operation. This three-phase AC/DC-DC/AC converter system developed for UPS can achieve the 1.8% higher efficiency and 20dB lower conduction noise than those of the conventional three-phase hard-switching PWM AC/DC-DC/AC converter system. It is proved that actual efficiency of the proposed three-phase AC/DC-DC/AC converter system operating under a condition of soft switching is 88.7% under 10kw output power.

• Journal of Power Electronics
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• 제3권1호
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• pp.1-9
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• 2003

This paper presents a performance analysis of typical Auxiliary Resonant Commutation Snubber-assisted three phase voltage source soft switching inverter which can operate under a condition of Zero Voltage Switching (ZVS) using a digital control scheme which is suitable for high power applications compared with resonant DC link snubber assisted soft switching inverter. The system performances of this inverter are illustrated and evaluated on the basis of experimental results.

• 정보통신설비학회논문지
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• 제4권1호
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• pp.7-13
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• 2005

In this paper, we propose the time synchronization module on fiber optic repeater to use optic line delay for obtaining time synchronization between up-link and down-link, in the 2.3 GHz WiBro network using TDD/OFDM (Time Division Duplex/Orthogonal Frequency Division Multiplexing) Generally, when we use fiber optic repeater to remove the shade area, it occurs transmission delay which is caused by optic transmission between RAS (Radio Access Station) and fiber optic repeater and inner delay of fiber optic repeater. Because the WiBro system is adopting a TOO method and there exists the difference of switching time which is caused by these delay between up-link and down-link, it occurs ISI (Inter Symbol Interference), ICI (Inter Carrier Interference). These interference results in the reduction of the coverage. And the inconsistency between Up-Link and Down-Link switching time maybe gives rise to the interruption of communication. In order to prevent these cases, we propose synchronization module using analog optic line delay as the one of synchronizing up-link and down-link. And we propose the consideration factor for the designing time synchronization module and the feature of optic line of analog method. The measurement result of optic line time synchronization module of structure proposed is as follows, the delay error of $0.5{\mu}g$ and the insertion loss value below maximum 4.5dB in range of $0{\sim}40{\mu}s$. These results fully meet the specification of WiBro System.

• KSII Transactions on Internet and Information Systems (TIIS)
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• 제7권4호
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• pp.651-669
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• 2013

In this paper, we study a novel routing algorithm based on load balancing for multi-channel wireless mesh networks. In order to increase the network capacity and reduce the interference of transmission streams and the communication delay, on the basis of weighted cumulative expected transmission time (WCETT) routing metric this paper proposes an improved routing metric based on load balancing and channel interference (LBI_WCETT), which considers the channel interference, channel diversity, link load and the latency brought by channel switching. Meanwhile, in order to utilize the multi-channel strategy efficiently in wireless mesh networks, a new channel allocation algorithm is proposed. This channel allocation algorithm utilizes the conflict graph model and considers the initial link load estimation and the potential interference of the link to assign a channel for each link in the wireless mesh network. It also utilizes the channel utilization percentage of the virtual link in its interference range as the channel selection standard. Simulation results show that the LBI_WCETT routing metric can help increase the network capacity effectively, reduce the average end to end delay, and improve the network performance.

• Journal of Power Electronics
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• 제14권6호
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• pp.1178-1188
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• 2014

This study proposes a finite-state model predictive controller to regulate the load current and balance the DC-link capacitor voltages of a four-leg neutral-point-clamped converter. The discrete-time model of the converter, DC-link, inductive filter, and load is used to predict the future behavior of the load currents and the DC-link capacitor voltages for all possible switching states. The switching state that minimizes the cost function is selected and directly applied to the converter. The cost function is defined to minimize the error between the predicted load currents and their references, as well as to balance the DC-link capacitor voltages. Moreover, the current regulation performance is improved by using a two-step prediction horizon. The feasibility of the proposed predictive control scheme for different references and loads is verified through real-time implementation on the basis of dSPACEDS1103.

• Journal of Communications and Networks
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• 제10권3호
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• pp.351-361
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• 2008

This paper presents a delay-margin based traffic engineering (TE) approach to provide end-to-end quality of service (QoS) in multi-protocol label switching (MPLS) networks using differentiated services (DiffServ) at the link level. The TE, including delay, class, and route assignments, is formulated as a nonlinear optimization problem reflecting the inter-class and inter-link dependency introduced by DiffServ and end-to-end QoS requirements. Three algorithms are used to provide a solution to the problem: The first two, centralized offline route configuration and link-class delay assignment, operate in the convex areas of the feasible region to consecutively reduce the objective function using a per-link per-class decomposition of the objective function gradient. The third one is a heuristic that promotes/demotes connections at different links in order to deal with concave areas that may be produced by a trunk route usage of more than one class on a given link. Approximations of the three algorithms suitable for on-line distributed TE operation are also derived. Simulation is used to show that proposed approach can increase the number of users while maintaining end-to-end QoS requirements.

• Journal of Power Electronics
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• 제14권4호
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• pp.764-777
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• 2014

This study analyzes the mathematical relationship between DC-link voltage and system parameters for shunt active power filters (APFs). Analysis and mathematical deduction are used to determine the required minimum DC-link voltage for APF. A novel adaptive DC-link voltage controller for the three-phase four-wire shunt APF is then proposed. In this controller, the DC-link voltage reference value will be maintained at the required minimum voltage level. Therefore, power consumption and switching loss will effectively decrease. The DC-link voltage can also adaptively yield different DC-link voltage levels based on different harmonic currents and grid voltage levels and thus avoid the effects of harmonic current and grid voltage fluctuation on compensation performance. Finally, representative simulation and experimental results in a three-phase four-wire center-split shunt APF are presented to verify the validity and effectiveness of the minimum DC-link voltage design and the proposed adaptive DC-link voltage controller.

• Journal of Power Electronics
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• 제17권1호
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• pp.106-114
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• 2017

In this paper, the Selective Harmonic Mitigation-PWM (SHM-PWM) method is used in single-phase and three-phase Cascaded H-Bridge (CHB) inverters in order to fulfill different power quality standards such as EN 50160, CIGRE WG 36-05, IEC 61000-3-6 and IEC 61000-2-12. Non-equal DC link voltages are used to increase the degrees of freedom for the proposed SHM-PWM technique. In addition, it will be shown that the obtained solutions become continuous and without sudden changes. As a result, the look-up tables can be significantly reduced. The proposed three-phase modulation method can mitigate up to the 50th harmonic from the output voltage, while each switch has just one switching in a fundamental period. In other words, the switching frequency of the power switches are limited to 50 Hz, which is the lowest switching frequency that can be achieved in the multilevel converters, when the optimal selective harmonic mitigation method is employed. In single-phase mode, the proposed method can successfully mitigate harmonics up to the 50th, where the switching frequency is 150 Hz. Finally, the validity of the proposed method is verified by simulations and experiments on a 9-level CHB inverter.

• Journal of Electrical Engineering and Technology
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• 제13권4호
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• pp.1528-1538
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• 2018

In this paper, configuration of $1-{\phi}$ seven-level boost DC-link cascade based reversing voltage multilevel inverter (BDCLCRV MLI) is proposed for uninterrupted power supply (UPS) applications. It consists of three level boost converter, level generation unit and full bridge circuit for polarity generation. When compared with conventional boost cascaded H-bridge MLI configurations, the proposed system results in reduction of DC sources, reduced power switches and gate drive requirements. Inverter switching is accomplished by providing appropriate switching angles that is generated by any optimization switching angle techniques. Here, round modulation control (RMC) method is taken as the optimization method and switching angles are derived and the same is compared with various switching angles methods i.e., equal-phase (EP) method, and half-equal-phase (HEP) method which results in improved quality of obtained AC power with lowest total harmonic distortion (THD). Reduction in DC sources and switch count makes the system more cost effective. A simulation and prototype model of $1-{\phi}$ seven-level BDCLCRV MLI system is developed and its performance is analyzed for various operating conditions.