• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.2 s.344
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• pp.76-83
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• 2006

We proposed a new level shifter circuit architecture. The prposed circuit can provide high output voltage upto 15V by taking 3.3V logic signal compared to the conventional level shifter. The unposed circuit has compatible speed, low power consumption and chip size. We have confirmed the operation by conducting HSPICE simulation.

• 한국정보디스플레이학회:학술대회논문집
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• 2006.08a
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• pp.1279-1282
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• 2006

An ultra low-power down-conversion level shifter using low temperature poly-crystalline silicon thin film transistors is proposed for mobile applications. The simulation result shows that the power consumption of the proposed circuits is only 17% and the propagation delay is 48% of those of the conventional cross-coupled level shifter without additional area. And the measured power consumption is only 21% of that of the crosscoupled level shifter.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.657-658
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• 2006

A Novel level-shifter circuit for Display Panel Driver is presented. A Proposed level-shifter is for the high speed and high-voltage driving capability. In order to achieve this purpose, the proposed level-shifter restricts and separates the Vgs of the output driver's pull-up PMOS and pull-down NMOS with Zener diode. And a speed-up PMOS transistor is introduced to reduce delay. The control signal of speed-up PMOS was designed by bootstrapping method to minimize the gate to source (Vgs) voltage to avoid Vgs breakdown.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.26 no.1
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• pp.13-17
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• 2013

In this paper, we designed a charge pump circuit using level shifter for LED driver IC. The designed circuit makes the 15 V output voltage from the 5 V input in condition of 50 kHz switching frequency. The prototype chip which include the proposed charge pump circuit and its several internal sub-blocks such as oscillator, level shifter was fabricated using a 0.35 um 20 V BCD process technology. The size of the fabricated prototype chip is 2,350 um ${\times}$ 2,350 um. We examined performances of the fabricated chip and compared its measured results with SPICE simulation data.

• The Journal of the Korea institute of electronic communication sciences
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• v.11 no.5
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• pp.479-484
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• 2016

In this paper, a design of DC level shifter transmitting and receiving control and data signal which have various DC level through daisy chain interface between master IC and slave is introduced in the cell voltage monitoring (CVM). Circuit designed with a latch structure have a function to operate in high speed and for output of variable DC level through transmission gate. As a result of the simulation and the measurement, it was confirmed that control and data signal could be transferred according to the change of DC level from 0V to 30V. Delay time was measured about 170ns. but, it was considered as a negligible tolerance due to a parasitic capacitance of measuring probe and test board.

• Journal of Electrical Engineering and Technology
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• v.9 no.4
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• pp.1137-1144
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• 2014

A parallel-feeding AC traction power system increases the power supply capacity and decreases voltage fluctuations, but the circulating power flow caused by the phase difference between the traction substations prevents the system from being widely used. A circuit analysis shows that the circulating power flow increases almost linearly as the phase difference increases, which adds extra load to the system and results in increased power dissipation and load unbalance. In this paper, we suggest a phase shifter for the parallel-feeding AC traction power system. The phase shifter regulates the phase difference and the circulating power flow by injecting quadrature voltage which can be obtained directly from the Scott-connection transformer in the traction substation. A case study involving the phase shifter applied to the traction power system of a Korean high-speed rail system shows that a three-level phase shifter can prevent circulating power flow while the phase difference between substations increases up to 12 degrees, mitigate the load unbalance, and reduce power dissipation.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.525-526
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• 2008

This paper proposes a new high-speed level shifter using a special high voltage device with low threshold voltage. Also, novel low voltage swing method is proposed. The high voltage device is a standard LDMOS(Laterally Diffused MOS) device in a $0.18{\mu}m$ CMOS process without adding extra mask or process step to realize it. A level shifter uses 5V LDMOSs as voltage clamps to protect 1.8V NMOS switches from high voltage stress the gate oxide. Also, level-up transition from 1.8V to 5V takes only 1.5ns in time. These circuits do not consume static DC power, therefore they are very suitable for low-power and high-speed interfaces in the deep sub-quarter-micron CMOS technologies.

• 한국정보디스플레이학회:학술대회논문집
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• 2009.10a
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• pp.464-465
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• 2009

A new level shifter using n-channel aluminum-doped zinc tin oxide (AZTO) thin film transistors (TFTs) was proposed to integrate driving circuits on qVGA panels for mobile display applications. The circuit used positive feedback loop to overcome limitations of circuits designed with oxide TFTs which is depletion mode n-channel TFTs. The measured results shows that the proposed circuit shifts 10 V input voltage to 20 V output voltage and its power consumption is 0.46 mW when the supply voltage is 20 V and the operating frequency is 10 kHz.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.1
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• pp.180-184
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• 2013

In this paper, a low power antenna switch controller IC is designed using a silicon-on-insulator (SOI) CMOS technology. To improve power handling capability and harmonic distortion performance of the antenna switch, the proposed antenna switch controller provides 3-state logic level such as +VDD, GND, and -VDD for the gate and body of switch of FETs according to decoder signal. By employing input-coupled current ring oscillator and hardware efficient level shifter, the proposed controller greatly reduces power consumption and hardware complexity. It consumes 135 ${\mu}A$ at a 2.5 V supply voltage in active mode, and occupies $1.3mm{\times}0.5mm$ in area. In addition, it shows fast start-up time of 10 ${\mu}s$.

• Proceedings of the IEEK Conference
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• 2003.07a
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• pp.613-616
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• 2003

This paper describes the design and implementation of wideband 360$^{\circ}$ phase shifter by using I/Q vector method. One of four quadrants was selected by a switching operation and the desired phase value was obtained by varying attenuation level of attenuator located in I/Q path. The minimum phase RMS error of 3.6$^{\circ}$ and the maximum phase RMS error of 25.2$^{\circ}$ were measured over 6~180Hz frequency range. Those characteristics are good enough for the requirement of ECM radar equipment. The phase values can be adjusted by control module.