• Journal of Radiopharmaceuticals and Molecular Probes
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• v.8 no.2
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• pp.95-101
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• 2022

Microfluidic radioimmunoassay (RIA) platform called µ-RIA spends less reagent and shorter reaction time for the analysis compared to the conventional tube-based radioimmunoassay. This study reported the design of µ-RIA chips optimized for the gamma counter which could measure the small samples of radioactive materials automatically. Compared with the previous study, the µ-RIA chips developed in this study were designed to be compatible with conventional RIA test tubes. And, the automatic gamma counter could detect radioactivity from the ¹²⁵I labeled anti-PSA attached to the chips. Effects of the multi-layer microchannels and two-phase flow in the µ-RIA chips were investigated in this study. The measured radioactivity from the ¹²⁵I labeled anti-PSA was linearly proportional to the number of stacked chips, representing that the radioactivity in µ-RIA platform could be amplified by designing the chips with multi-layers. In addition, we designed µ-RIA chip to generate liquid-gas plug flow inside the microfluidic channel. The plug flow can promote binding of the biomolecules onto the microfluidic channel surface with recirculation in the liquid phase. The ratio of liquid slug and air slug length was 1 : 1 when the ¹²⁵I labeled anti-PSA and the air were injected at 1 and 35 µL/min, respectively, exhibiting 1.6 times higher biomolecule attachment compared to the microfluidic chip without the air injection. This experimental result indicated that the biomolecular reaction was improved by generating liquid-gas slugs inside the microfluidic channel. In this study, we presented a novel µ-RIA chips that is compatible with the conventional gamma counter with automated sampler. Therefore, high-throughput radioimmunoassay can be carried out by the automatic measurement of radioactivity with reduced radiowaste generation. We expect the µ-RIA platform can successfully replace conventional tube-based radioimmunoassay in the future.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.5 no.6
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• pp.1066-1072
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• 2001

ALOHA Multi-Carrier DS-CDMA systems in the multipath Rayleigh fading channel. The throughput of two systems are compared according to the length of a packet in the fast Rayleigh and the slow Rayleigh multipath fading. As a result, we have known that Multi-Carrier DS-CDMA system has less capacity than wideband DS-CDMA system in the same bandwidth, but throughput of Multi-Carrier DS-CDMA system is higher than that of wideband DS-CDMA system. And in Multi-Carrier DS-CDMA systems, higher throughput can be obtained through shortening the length of packet in the fast Rayleigh fading, and it is efficient to control the length of a packet adequately or increase the system capacity of Multi-Carrier DS-CDMA system in the slow Rayleigh fading.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2001.10a
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• pp.675-679
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• 2001

In this paper, throughput is derived for slotted ALOHA wideband DS-CDMA and slotted ALOHA Multi-Carrier DS-CDMA systems in the multipath Rayleigh fading channel. The throughput of two systems are compared according to the length of a packet in the fast Rayleigh and the slow Rayleigh multipath fading. As a result, we have known that Multi-Carrier DS-CDMA system has less capacity than wideband DS-CDMA system in the same bandwidth, but throughput of Multi-Carrier DS-CDMA system is higher than that of wideband DS-CDMA system. And in Multi-Carrier DS-CDMA systems, higher throughput can be obtained through shortening the length of packet in the fast Rayleigh fading and it is efficient to control the length of a packet adequately or increase the system capacity of Multi-Carrier DS-CDMA system in the slow Rayleigh fading.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.3 s.333
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• pp.1-8
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• 2005

In this paper, we analyzed the DC and RF characteristics of $0.1\;{\mu}m$ metamorphic high electron mobility transistor (MHEMT) using the ISE-TCAD simulation tool. we also analyzed the effects or the scaling on vertical and lateral dimensions such as a gate length, source-drain spacing, and channel thickness. We discussed the degradation of extrinsic transconductance $g_{m,max}$ in the MHEMTs adopting the gate length $(L_g)$ of $sub-0.1\;{\mu}m$. We suggested the model describing the effects on the vertical and lateral parameter scaling.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.295-298
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• 1999

AlGaAs/InGaAs power P-HEMTS (Pseudo-morphic High Electron Mobility Transistors) with 1.0-${\mu}{\textrm}{m}$ gate length for PCS applications have been fabricated. We adopted single heterojunction P-HEMT structure with two Si-delta doped layer to obtain higher current density. It exhibits a maximum current density of 512㎃/mm, an extrinsic transconductance of 259mS/mm, and a gate to drain breakdown voltage of 12.0V, respectively. The device exhibits a power density of 657㎽/mm, a maximum power added efficiency of 42.1%, a linear power gain of 9.85㏈ respectively at a drain bias of 6.0V, gate bias of 0.6V and an operation frequency of 1.765㎓.

• Proceedings of the KIEE Conference
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• 2002.11c
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• pp.601-604
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• 2002

In this paper, the timing do-skew modeling for a high speed logic tester channels is developed. The time delay of each channel in a logic tester are different from other channels and it can produce timing error in a test. To get the best timing accuracy in the test with a logic tester, the timing skew must be compensated. The timing skew of channels is due to the difference of time delay of pin-electronics devices composing channels and length of metal line placed on PCB. The expected timing difference of channels can be calculated according to the specifications of pin electronics devices and strip line modeling of PCB. With the calculated delay time, the timing skew compensation circuit has been designed. With the timing skew compensation circuit, the timing calibration of a logic tester can be peformed easily and automatically without other time measuring instruments. The calibration method can then be directly applied to logic testers in mass production lines.

• Journal of the Korean Institute of Telematics and Electronics
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• v.19 no.4
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• pp.38-48
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• 1982

Performance and realization of finite impulse response (FIR) digital filters that use an adaptive delta modulator (ADM) as an analog/digital converter have been studied. This filter requires no multiplication and offers many advantages over conventional PCM filters in low power consumption, small size, and cost effectiveness. Analytical formulas have been derived for the expected mean-squared errors and also for the word length necessary to achieve the desired performance. Computer simultation has been done to optimize the parameter values and to verify the results of performance analysis. In addition, design of FIR ADM digital filters for processing single and multi-channel signals has been considered.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.11
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• pp.2373-2377
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• 2009

In this paper, the threshold voltage characteristics have been analyzed using three dimensional Poisson's equation for FinFET. The FinFET is extensively been studing since it can reduce the short channel effects as the nano device. We have presented the short channel effects such as subthreshold swing and threshold voltage for PinFET, using the analytical three dimensional Poisson's equation. We have analyzed for channel length, thickness and width to consider the structural characteristics for FinFET. Using this model, the subthreshold swing and threshold voltage have been analyzed for FinFET since the potential and transport model of this analytical three dimensional Poisson's equation is verified as comparing with those of the numerical three dimensional Poisson's equation.

• Proceedings of the Korea Society of Information Technology Applications Conference
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• 2005.11a
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• pp.99-102
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• 2005

In the paper, a proposed VCO based on bondwire inductances and nMOS varactors was implemented in a standard $0.25\;{\mu}m$ CMOS process. Using the new drain current model and a propagation delay time model equations, the operation speed of CMOS gate will predict the dependence on the load capacitance and the depth of oxide, threshold voltage, the supply voltage, the channel length. This paper describes the result of simulation which calculated a gate propagation delay time by using new drain current model and a propagation delay time model. At the result, When the reverse bias voltage on the substrate changes from 0 voltage to 3 voltage, the propagation delay time is appeared the delay from 0.8 nsec to 1 nsec. When the reverse voltage is biased on the substrate, for reducing the speed delay time, a supply voltage has to reduce. The $g_m$ value of MOSFET is calculated by using new drain current model.

• 한국정보통신설비학회:학술대회논문집
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• 2009.08a
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• pp.190-196
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• 2009

In this paper, performance of a turbo-coded OFDM system is analyzed and simulated in a power line communication channel. Since the power line communication system typically operates in a hostile environment, turbo code has been employed to enhance reliability of transmitted data. The performance is evaluated in terms of bit error probability. As turbo decoding algorithms, MAP (maximum a posteriori), Max-Log-MAP, and SOVA (soft decision Viterbi output) algorithms are chosen and their performances are compared. From simulation results, it is demonstrated that Max-Log-MAP algorithm is promising in terms of performance and complexity. It is shown that performance is substantially improved by increasing the number of iterations and interleaver length of a turbo encoder. The results in this paper can be applied to OFDM-based high-speed power line communication systems.