• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.18 no.5
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• pp.401-406
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• 2005

Two dimensional MEDICI simulator is used to study the electrical characteristics of Dual Gate Emitter Switched Thyristor. The simulation is done in terms of the current-voltage characteristics with the variations of p-base impurity concentrations and current flow. Compared with the other power devices such as MOS Controlled Cascade Thyristor(MCCT), Conventional Emitter Switched Thyristor(C-EST) and Dual Channel Emitter Switched Thyristor(DC-EST), Dual Gate Emitter Switched Thyristor(DG-EST) shows to have tile better electrical characteristics, which is the high latch-up current density and low forward voltage-drop. The proposed DG-EST which has a non-planer u-base structure under the floating N+ emitter indicates to have the better characteristics of latch-up current and breakover voltage in spite of the same turn-off characteristics.

• Transactions on Electrical and Electronic Materials
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• v.2 no.4
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• pp.15-18
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• 2001

A new small scaling Lateral Trench Insulated Gate Bipolar Transistor (SSLTIGBT) was proposed to improve the characteristics of the device. The entire electrode of the LTIGBT was replaced with a trench-type electrode. The LTIGBT was designed so that the width of device was no more than 10 ${\mu}{\textrm}{m}$. The latch-up current densities were improved by 4.5 and 7.6 times, respectively, compared to those of the same sized conventional LTIGBT arid the conventional LTIGBT which has the width of 17 ${\mu}{\textrm}{m}$. The enhanced latch-up capability of the SSLTIGBT was obtained due to the fact that the hole current in the device reaches the cathode via the p+ cathode layer underneath the n+ cathode layer, directly. The forward blocking voltage of the SSLTIGBT was 125 V. At the same size, those of the conventional LTIGBT and the conventional LTIGBT with the width of 17 ${\mu}{\textrm}{m}$ were 65 V and 105 V, respectively. Because the proposed device was constructed of trench-type electrodes, the electric field In the device were crowded to trench oxide. Thus, the punch through breakdown of LTEIGBT occurred late.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.38 no.11
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• pp.1215-1220
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• 2014

Breaking time is an important performance indicator of a circuit breaker. Thus, the operating mechanism of the circuit breaker should be optimized for reducing the breaking time. The operating mechanism in a gas circuit breaker is made up of several latches. Specifically, the geometry and relative positions of latches influence the dynamic behaviors of the operating mechanism. In this study, a three-stage latch operating mechanism is analyzed on the basis of the verified multibody dynamics model constructed using the MSC.ADAMS program. The relative positions and lengths of latches are selected as design variables. The dominant design variables are selected by a design study. Optimization is performed using a genetic algorithm (GA). The study results demonstrate that the performance of the circuit breaker improves by about 22.5.

• Journal of IKEEE
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• v.2 no.1 s.2
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• pp.101-107
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• 1998

This paper is studied micro-defect characteristics by phosphorus 1MeV ion implantation and Rs, SRP, SIMS, XTEM for the RTA process was measured and simulated. As the dose is higher, the Rs is lower. When the dose are $1{\times}10^{13}/cm^2,\;5{\times}10^{13}/cm^2,\;1{\times}10^{14}/cm^2$, the Rp are $1.15{\mu}m,\;1.15{\mu},\;1.10{\mu}m$ respectively. As the RTA time is longer, the maximum concentration position is deeper from the surface and the concentration is lower. Before the RTA was done, we didn't observe any defect. But after the RTA process was done, we could observe the RTA process changed the micro-defects into the secondary defects. The simulation using the buried layer and connecting layer structure was performed. As results, the connecting layer had more effect than the buried layer to latch-up immune. Trigger current was more $0.6mA/{\mu}m$ and trigger voltage was 6V at dose $1{\times}10^{14}/cm^2$ and the energy 500KeV of connecting layer Lower connecting layer dose, latch-up immune characteristics was better.

• Proceedings of the KIEE Conference
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• 2007.07a
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• pp.1315-1316
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• 2007

This is paper, a new structure to effectively improve the Vce(sat) voltage and latch-up current in NPT type IGBTs with hole barrier layer and diverter. The hole barrier layer acts as a barrier to prevent the holes from flowing into the p-layer and stores them in the n-layer. And the diverter significantly reduce hole current from flowing into the p-layer and improve latch up current. Analysis on the Breakdown voltage shows identical values compared to existing Conventional IGBT structures. This shows an improvement on Vce(sat) and Latct-up current without lowering other characteristics of the device. The electrical characteristics were studied by MEDICI simulation results.

• Proceedings of the KIPE Conference
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• 2018.07a
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• pp.539-548
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• 2018

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.27 no.10
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• pp.75-79
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• 2013

The automatic quiescent power cut-off receptacles(QPCR from now on) have achieved a noticeable energy saving so far. The government is preparing a new code for wider promotion of the QPCRs. This paper presents a new QPCR that adopts the latch relay instead of the conventional coil-operated relay. Measurement results of the prototype have shown up to 0.22W improvement of quiescent power compared with existing products.

• Journal of the Korean Institute of Telematics and Electronics
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• v.21 no.5
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• pp.46-54
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• 1984

A silicon-gate n-well CMOS process with 3 $\mu$m gate length was developed and its possibility for the applications was discussed,. Threshold voltage was easily controlled by ion implantation and 3-$\mu$m gate length with 650 $\AA$ oxide shows ignorable short channel effect. Large value of Al-n+ contact resistance is one of the problems in fabrications of VLSI circuits. Transfer characteristics of CMOS inverter is fairly good and the propagation delay time per stage in ring oscillator with layout of (W/L) PMOS /(W/L) NMOS =(10/5)/(5/5) is about 3.4 nsec. catch-up occurs on substrate current of 3-5 mA in this process and critically dependent on the well doping density and nt-source to n-well space. Therefore, research, more on latch-up characteristics as a function of n-well profile and design rule, especially n+-source to n-well space, is required.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.805-808
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• 2005

In this study, the design of advanced LVDS(Low Voltage Differential Signaling) I/O interface circuit with new structural low triggering ESD(Electro-Static Discharge) protection circuit was investigated. Due to the differential transmission technique and low power consumption at same time. maximum transmission data ratio of designed LVDS transmitter was simulated to 5Gbps, Also, the LIGCSCR(Latch-up Immune Gate Coupled SCR)was designed. It consists of PLVTSCR (P-type Low Voltage Trigger SCR), control NMOS and RC network. The triggering voltage was simulated to 3.6V. And the latch-up characteristics were improved. Finally, we performed the layout high speed I/O interlace circuit with the low triggered ESD protection device in one-chip.

• Transactions on Electrical and Electronic Materials
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• v.5 no.4
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• pp.129-132
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• 2004

The electrothermal characteristics of a high voltage LIGBT(Lateral Insulated Gate Bipolar Transistor) using thin silicon on insulator (SOI) and silicon on sapphire (SOS) such as thermal conductivity and sink is analyzed by MEDICI. The device simulations demonstrate that the thermal conductivity of the buried oxide is an important parameter for modeling of the thermal behavior of SOI devices. In this paper we simulated the thermal conductivity and temperature distribution of a SOI LIGBT with an insulator layer of SiO$_2$ and $Al_2$O$_3$ at before and after latch-up and verified that the SOI LIGBT with the $Al_2$O$_3$ insulator had good thermal conductivity and reliability.