• The Transactions of the Korean Institute of Electrical Engineers P
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• v.62 no.2
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• pp.84-89
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• 2013

In this paper, we propose interface circuits for reducing power consumption and EMI when sequences of data from LCD controller to LCD driver IC by transmitting two bit data during one clock period. The proposed circuits are operated in current mode, which is different from conventional voltage-mode signaling techniques, and also employ threshold technique of Modified-LVDS(Low Voltage Differential Signaling) method. We have simulated the proposed circuits using H-SPICE tool for performance analysis of the proposed method. The simulation results show that the proposed circuits provide a faster transmission speed and stronger noise immunity than the conventional LVDS circuits. It might be suitable for the real-time transmission of huge image data in LCD system.

• The Journal of the Acoustical Society of Korea
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• v.38 no.2
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• pp.240-245
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• 2019

This paper is a study result on long distance transmission of underwater acoustic sensor data over cable. The data transceiver is designed using the LVDS (Low Voltage Differential Signaling) transmission scheme, and the jitter characteristics are analyzed by measuring the long distance transmission signal through the cable. In order to reduce the jitter, a pre-emphasis technique is applied to compensate the transmitting signal to be attenuated by long distance transmission, and the transmission characteristics were verified according to the distance.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.5
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• pp.879-886
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• 2008

This paper addresses the analysis and the design optimization of differential interconnects for Low-Voltage Differential Signaling (LVDS) applications. Thanks to the differential transmission and the low voltage swing, LVDS offers high data rates and improved noise immunity with significantly reduced power consumption in data communications, high-resolution display, and flat panel display. We present an improved model and new equations to reduce impedance mismatch and signal degradation in cascaded interconnects using optimization of interconnect design parameters such as trace width, trace height and trace space in differential flexible printed circuit board (FPCB) transmission lines. We have carried out frequency-domain full-wave electromagnetic simulations, time-domain transient simulations, and S-parameter simulations to evaluate the high-frequency characteristics of the differential FPCB interconnects. The 10% change in trace width produced change of approximately 6% and 5.6% in differential impedance for trace thickness of $17.5{\mu}m$ and $35{\mu}m$, respectively. The change in the trace space showed a little change. We believe that the proposed approach is very helpful to optimize high-speed differential FPCB interconnects for LVDS applications.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.6 no.7
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• pp.1069-1072
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• 2002

고도로 발달된 정보화 시대에서 우리가 원하는 정보를 짧은 시간, 적은 비용으로 서로 주고 받기 위해서는 이것에 맞는 시스템이 요구된다. 반도체 chip의 대용량과 고속화됨으로써 TTL, ,LVTTL등이 data 100Mbps 정도를 안전하게 전달 할 수 있는 능력이 있으므로 그 이상을 전달할 수 있는 새로운 Logic level이 필요하게 되었다. 이에 맞추어 신호 level의 여러 가지 중 본 논문에서는 Virtex II XC2V 1000 FF896을 이용하여 Differential I/O LVDS( Low Voltage Differential Signaling ) level 특성을 clock, Data와의 전송관계를 Eye_Pattern을 통해 살펴보았다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2002.11a
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• pp.473-476
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• 2002

고도로 발달된 정보화 시대에서 우리가 원하는 정보를 짧은 시간, 적은 비용으로 서로 주고받기 위해서는 이것에 맞는 시스템이 요구된다. 반도체 chip의 대용량과 고속화됨으로써 TTL, LVTTL 등이 data 100Mbps 정도를 안전하게 전달 할 수 있는 능력이 있으므로 그 이상을 전달할 수 있는 새로운 Logic level이 필요하게 되었다. 이에 맞추어 신호 level의 여러 가지 중 본 논문에서는 Virtex II XC2V 1000 FF896을 이용하여 Differential I/O LVDS(Low Voltage Differential Signaling) level 특성을 clock, Data와의 전송 관계를 Eye_Pattern을 통해 살펴보았다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.8 s.338
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• pp.1-6
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• 2005

A dual-level low voltage differential signalling (DLVDS) circuit is proposed aiming at reducing transmission lines for LCD driver IC. In the proposed circuit, we apply a couple of primitive data to DLVDS circuit as inputs. The transmitter converts two inputs to two kinds of fully differential level signals. In this circuit, two transmission lines are sufficient to transfer two primitive inputs while keeping the LVDS feature. The receiver recovers The original input data through a level decoding circuit. We fabricated the proposed circuit using $0.25\mu m$ CMOS technology. The resultant circuit shows 1-Gbps/2-line data rate and 35-mW power consumption at 2.5V supply voltage, respectively.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.5
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• pp.1089-1094
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• 2013

In this study, we propose how th implement a MDDI(Mobile Display Digital Interface) protocol packet generation method in software. MDDI protocol is widely used in mobile display device. MDDI protocol packets are generated by software within micro processor. This method needs the minimum hardware configuration. In order to implementation of this method, we design a hardware platform with a high performance microprocessor and a FPGA. The packets generated by software within microprocessor are converted into LVDS signals, and transmitted by hardware within FPGA. This study suggests the benefits of the way how software can easily create a variety of packet. But, this proposed method takes more time in packet transmission compared to the traditional method. This weakness remains as a future challenge, which can be soon improved.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.9
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• pp.7-13
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• 2009

This paper presents a multi-channel transceiver that achieves a data rate of 3.125Gb/s/ch. The LVDS is used because of its noise immunity and low power consumption. And a pre-emphasis circuit is also proposed to increase the transmitter speed. On the receiver side, a low-power CDR(clock and data recovery) using 1/4-rate clock based on dual-interpolator is proposed. The CDR generates needed additional clocks in each recovery part internally using only inverters. Therefore each part can be supplied with the same number of 1/4-rate clocks from a clock generator as in 1/2-rate clock method. Thus, the reduction of a clock frequency relaxes the speed limitation and lowers power dissipation. The prototype chip is comprised of two channels and was fabricated in a $0.18{\mu}m$ standard CMOS process. The output jitter of transmitter is loops, peak-to-peak(0.31UI) and the measured recovered clock jitter is 47.33ps, peak-to-peak which is equivalent to 3.7% of a clock period. The area of the chip is $3.5mm^2$ and the power consumption is about 119mW/ch.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2012.10a
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• pp.689-691
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• 2012

In this study, a MDDI protocol packet generation method that is implemented in software is proposed. MDDI protocol is used widely for display device. In this study, MDDI protocol packets are generated by software within micro processor. This method needs minimum hardware configuration. For implementation of this method, we design a hardware platform with a high performance microprocessor and a FPGA. The packets generated by software within microprocessor is converted into LVDS signals, and transmitted by hardware within FPGA.

• Proceedings of the KIEE Conference
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• 2007.10a
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• pp.273-274
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• 2007

최근에 각광받는 영상표시 장치인 LCD와 PDP는 Progressive 방식으로 영상을 표시하며 화질 또한 SD에서 HD로 바뀌었다. 따라서 대용량의 데이터를 빠른 시간에 FPD 패널로 전송해야 하며 이를 위해 LVDS 전송 방법을 사용한다. 대부분의 화질 테스트 장비들은 빠른 데이터 전송을 위해 내부에 저장되어 있는 특정 패턴들만 LVDS 신호로 바꾸어 패널로 전송하게 되며 저장되어 있는 영상을 움직이는 것도 제한적이다. 하지만 LCD 패널의 응답속도, PDP 패널의 DFC등을 테스트 하기 위해서는 다양한 패턴이 필요하며 영상의 움직임 또한 자유롭게 조절할 수 있어야 한다. 따라서 본 논문에서는 다양한 패턴을 다운로드받아서 표시할 수 있는 테스트 장비를 설계하고 USB를 통해 테스트 장치 컨트롤 및 이미지 다운로드를 할 수 있는 프로그램을 설계하여 고정세 FPD의 화질을 테스트 할 수 있는 시스템을 구현하고자 한다.