• 센서학회지
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• 제13권6호
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• pp.436-445
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• 2004

In this study, a uroflowmetry system was developed to detect a voiding symptom conveniently at home or hospital. A implemented hardware was composed of mechanism and system circuit part, the software was developed to process uroflow data, graph display, extraction of parameter, and evaluation of congregate rate so as to analysis obtaining uroflow data. The following experiment was performed to evaluate an ability of classification and fitness. The curve pattern of uroflow was classified into each symptom. Various parameters were calculated in the curve pattern of each uroflow as follows. The parameters are MFR, AFR, VOL, VT, and FT. A significant difference among parameters was examined by a statistical analysis for extracted parameters between normal and abnormal experimental group. The uroflow data with the various symptom was divided into normal and abnormal group using fuzzy classifier. The result of the fuzzy classification using MFR and AFR was superior by 91.23 % than grouping evaluation including VOL.

• 한국콘텐츠학회논문지
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• 제13권4호
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• pp.44-52
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• 2013

SIFT(Scale Invariant Feature Transform) 알고리즘은 현재 비디오 감시카메라, 자율 주행시스템 등과 같은 영상 시스템에서 많이 사용되고 있다. SIFT 알고리즘에서 연산량과 연산시간이 가장 많이 필요한 부분이 descriptor의 sin/cos 함수를 연산하는 부분이다. 그러므로 본 논문에서는 SIFT 알고리즘에 사용되는 descriptor를 위한 sin/cos 함수를 하드웨어로 구현하였다. Verilog-HDL 언어를 사용하여 FPGA로 구현하고 그 성능을 분석한다. Xilinx Spartan 2E(XC2S200E-PQ208-6) 를 사용하여 구현하였을때, 149 Slices에 233 LUTs가 소모되었으며, 최대 주파수는 60.01MHz로 동작하였다. 또한 descriptor에 적용하여 소프트웨어와 비교 하였을 때 40배 정도의 빠른 성능 향상을 얻었다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제16권4호
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• pp.436-442
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• 2016

An electroencephalogram (EEG)-connectome processor to monitor and diagnose mental health is proposed. From 19-channel EEG signals, the proposed processor determines whether the mental state is healthy or unhealthy by extracting significant features from EEG signals and classifying them. Connectome approach is adopted for the best diagnosis accuracy, and synchronization likelihood (SL) is chosen as the connectome feature. Before computing SL, reconstruction optimizer (ReOpt) block compensates some parameters, resulting in improved accuracy. During SL calculation, a sparse matrix inscription (SMI) scheme is proposed to reduce the memory size to 1/24. From the calculated SL information, a small world feature extractor (SWFE) reduces the memory size to 1/29. Finally, using SLs or small word features, radial basis function (RBF) kernel-based support vector machine (SVM) diagnoses user's mental health condition. For RBF kernels, look-up-tables (LUTs) are used to replace the floating-point operations, decreasing the required operation by 54%. Consequently, The EEG-connectome processor improves the diagnosis accuracy from 89% to 95% in Alzheimer's disease case. The proposed processor occupies $3.8mm^2$ and consumes 1.71 mW with $0.18{\mu}m$ CMOS technology.

• KSII Transactions on Internet and Information Systems (TIIS)
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• 제16권8호
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• pp.2816-2830
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• 2022

Number Theoretic Transform (NTT) is a method to design efficient multiplier for large integer multiplication, which is widely used in cryptography and scientific computation. On top of that, it has also received wide attention from the research community to design efficient hardware architecture for large size RSA, fully homomorphic encryption, and lattice-based cryptography. Existing NTT hardware architecture reported in the literature are mainly designed based on radix-2 NTT, due to its small area consumption. However, NTT with larger radix (e.g., radix-4) may achieve faster speed performance in the expense of larger hardware resources. In this paper, we present the performance evaluation on NTT architecture in terms of hardware resource consumption and the latency, based on the proposed radix-2 and radix-4 technique. Our experimental results show that the 16-point radix-4 architecture is 2× faster than radix-2 architecture in expense of approximately 4× additional hardware. The proposed architecture can be extended to support the large integer multiplication in cryptography applications (e.g., RSA). The experimental results show that the proposed 3072-bit multiplier outperformed the best 3k-multiplier from Chen et al. [16] by 3.06%, but it also costs about 40% more LUTs and 77.8% more DSPs resources.

• 반도체디스플레이기술학회지
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• 제21권4호
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• pp.27-32
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• 2022

RISC-V is an open instruction set architecture (ISA) developed in 2010 at UC Berkeley, and active research is being conducted as a processor to compete with ARM. In this paper, we propose an SoC system including an RV32I ISA-based 32-bit 5-stage pipeline processor and AHB bus master. The proposed RISC-V processor supports 37 instructions, excluding FENCE, ECALL, and EBREAK instructions, out of a total of 40 instructions based on RV32I ISA. In addition, the RISC-V processor can be connected to peripheral devices such as BRAM, UART, and TIMER using the AHB-lite bus protocol through the proposed AHB bus master. The proposed SoC system was implemented in Arty A7-35T FPGA with 1,959 LUTs and 1,982 flip-flops. Furthermore, the proposed hardware has a maximum operating frequency of 50 MHz. In the Dhrystone benchmark, the proposed processor performance was confirmed to be 0.48 DMIPS.

• 센서학회지
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• 제32권4호
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• pp.246-251
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• 2023

Internet of Things (IoT) systems process signals from various sensors using signal processing algorithms suitable for the signal characteristics. To analyze complex signals, these systems usually use signal processing algorithms in the frequency domain, such as fast Fourier transform (FFT), filtering, and short-time Fourier transform (STFT). In this study, we propose a multi-mode sensor signal processor (SSP) accelerator with an FFT-based hardware design. The FFT processor in the proposed SSP is designed with a radix-2 single-path delay feedback (R2SDF) pipeline architecture for high-speed operation. Moreover, based on this FFT processor, the proposed SSP can perform filtering and STFT operation. The proposed SSP is implemented on a field-programmable gate array (FPGA). By sharing the FFT processor for each algorithm, the required hardware resources are significantly reduced. The proposed SSP is implemented and verified on Xilinxh's Zynq Ultrascale+ MPSoC ZCU104 with 53,591 look-up tables (LUTs), 71,451 flip-flops (FFs), and 44 digital signal processors (DSPs). The FFT, filtering, and STFT algorithm implementations on the proposed SSP achieve 185x average acceleration.

• Parasites, Hosts and Diseases
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• 제54권2호
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• pp.123-132
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• 2016

Trichomonas vaginalis causes the most prevalent sexually transmitted infection worldwide. Trichomonads have been detected in prostatic tissues from prostatitis, benign prostatic hyperplasia (BPH), and prostate cancer. Chronic prostatic inflammation is known as a risk factor for prostate enlargement, benign prostatic hyperplasia symptoms, and acute urinary retention. Our aim was to investigate whether T. vaginalis could induce inflammatory responses in cells of a benign prostatic hyperplasia epithelial cell line (BPH-1). When BPH-1 cells were infected with T. vaginalis, the protein and mRNA of inflammatory cytokines, such as CXCL8, CCL2, IL-$1{\beta}$, and IL-6, were increased. The activities of TLR4, ROS, MAPK, JAK2/STAT3, and NF-${\kappa}B$ were also increased, whereas inhibitors of ROS, MAPK, PI3K, NF-${\kappa}B$, and anti-TLR4 antibody decreased the production of the 4 cytokines although the extent of inhibition differed. However, a JAK2 inhibitor inhibited only IL-6 production. Culture supernatants of the BPH-1 cells that had been incubated with live T. vaginalis (trichomonad-conditioned medium, TCM) contained the 4 cytokines and induced the migration of human monocytes (THP-1 cells) and mast cells (HMC-1 cells). TCM conditioned by BPH-1 cells pretreated with NF-${\kappa}B$ inhibitor showed decreased levels of cytokines and induced less migration. Therefore, it is suggested that these cytokines are involved in migration of inflammatory cells. These results suggest that T. vaginalis infection of BPH patients may cause inflammation, which may induce lower urinary tract symptoms (LUTS).

• Journal of Acupuncture Research
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• 제23권4호
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• pp.101-113
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• 2006

Objectives : This study was designed to evaluate the effect of electroacupuncture at ciliao(BL32) on voiding pattern and uroflowmetry of patients with functional voiding disease. Methods Subjects were voluntarily recruited by newspaper·s and internet. All the subjects were confirmed as International Prostatism Symptom Score(IPSS), uroflowmetry, voiding diary, symptom. The acupuncture therapy was performed 3 times a week for 3 weeks by oriental medical doctor at hospital. Acupuncture points were BL32. The patient's symptoms were assessed before and after 3 weeks treatments by IPSS. Uroflowmetry for 5minutes and voiding diary for 48 hours was measured before and after 3 weeks treatments. Results : The results were as follows; 1. After 3 weeks compared to the pre-treatment, IPSS(QOL) scores were significantly unproved. 2. After 3 weeks compared to the pre-treatment, mean voiding volume, min voiding volume and mean voiding time on voiding daiary was significantly improved. 3. After 3 weeks compared to the pre-treatment, max flow velocity and mean flow velocity on uroflowmetry in spite of increase of voiding volume show a statistically significant difference. 4. Acupunctue had hardly some side effect compared to operation and medicines and was economical. Conclusion : This study suggests that acupuncture treatments can be applicable to improve symptoms in the patients with functional voiding disease. Further study on the acupuncture and other acupoints in the patients with functional voiding disease is recommended.

• 전기전자학회논문지
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• 제15권2호
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• pp.113-121
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• 2011

본 논문은 디스플레이포트의 보조채널에서 고속 데이터 전송을 할 수 있는 고속 양방향 보조 채널을 구성하기 위한 새로운 송 수신기 구조를 제안하고 적용에 대해 서술하였다. 제안된 고속 보조 채널은 저속 전송에서 맨체스터 인코딩을 사용하여 1Mbps대역폭을, 고속 전송에서 8B/10B인코딩 방식을 사용하여 720Mbps의 대역폭을 지원한다. 맨체스터 전송을 사용하여 고속 보조채널 및 메인링크의 링크 서비스 및 디바이스 서비스를 위한 저속 보조채널 블록을 제안하고, 8B/10B인코딩 방식을 통하여 보조채널을 통한 고속 데이터 전송을 위한 블록을 제안한다. 또한 데이터 패킷 구조와 데이터 전송방식에 대하여 정의하였다. 설계된 시스템은 Verilog HDL로 설계 되었으며, 고속 보조채널 송 수신기는 Xilinx Vertex4 FPGA을 사용하여 합성한 결과 7,648개의 LUTs와 6,020개의 registers를 사용 하였으며, 최대 동작 속도는 203MHz의 성능을 확인 하였다.

• 한국멀티미디어학회논문지
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• 제15권10호
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• pp.1247-1256
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• 2012

필터를 기반으로 하는 영상 처리 알고리즘은 많은 연산과 메모리 접근으로 인해 임베디드 환경에서의 실시간 동작이 어렵다. 본 논문에서는 필터 기반의 얼굴 검출 하드웨어 엔진을 임베디드 환경에서 실시간으로 동작시키기 위해 파이프라인 구조로 설계하고 검증하였다. 얼굴 검출 알고리즘은 입력으로 들어온 영상에서 학습된 얼굴의 특징 데이터를 이용하여 얼굴의 위치를 찾는 연산을 수행한다. 이를 하드웨어로 구현하기 위해 알고리즘의 연산을 파악하여 중복되는 연산을 병렬 처리하고 라인 메모리를 이용하여 메모리 접근을 최소화하여, 이것을 기반으로 파이프라인 구조의 하드웨어를 설계하였다. 하드웨어 구조는 Resize, ICT(Improved Census Transform), Find Candidate 등의 3 단계로 나뉘어져 있으며, 총 507KByte의 내부 SRAM을 사용하였다. ARM Cortex A8 프로세서와 Xilinx사의 Virtex5LX330을 이용하여 검증한 결과 9,039 LUTs를 사용하였고 최대 동작 클록은 165MHz로, VGA($640{\times}480$) 해상도에서 108 frame/sec의 동작속도로 최대 20명까지 검출이 가능한 것을 확인하였다.