• 한국정보디스플레이학회:학술대회논문집
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• 2006.08a
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• pp.218-221
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• 2006

In this paper, a high-voltage generator with several mA draw output currents using LTPS-TFT technology is proposed. The new generator can be efficiently boosted about +18V output voltages with 5mA draw output currents and power efficiency ${\eta}$ is around 84% under the conditions of +5V power-supply voltage and 250kHz frequency.

• 한국정보디스플레이학회:학술대회논문집
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• 2006.08a
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• pp.1791-1794
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• 2006

For system-on-glass (SoG) with low-temperature poly-silicon (LTPS) thin film transistor (TFT), a new system interface architecture and timing controller are developed. With the newly developed system interface architecture, line memory can be eliminated which would take large area of SoG display panel. The system interface and timing controller are targeted for the application for 6-bit gray scale, 60-frames/s qVGA format.

• 한국정보디스플레이학회:학술대회논문집
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• 2006.08a
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• pp.45-48
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• 2006

Effectiveness and its possibility of ELA (Excimer Laser Annealing) for advanced Si TFT system on insulator are described. Currently, extensive study is carried out to realize an advanced SoG (System on Glass) based on LTPS (Low Temperature Poly-Si) technique. By reducing further the process temperature and by improving the fabrication process of LTPS, addressing TFT circuits for FPD (Flat Panel Display) can be mounted onto a flexible plastic as well as onto a glass substrate. Functional devices on the insulating panels are developed to be formed by using ELA. Although technical issues are remained for the fabrication process, Si transistors including 3D TFT structure formed by ELA is expected as a functional Si system on insulator in the ubiquitous IT era.

• Information Display
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• v.2 no.1
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• pp.30-35
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• 2001

• Information Display
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• v.12 no.4
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• pp.15-23
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• 2011

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.9
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• pp.54-58
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• 2007

Development of high performance LTPS TFTs contributed to open up new SOP technology with various digital circuits integrated in display panels. This work introduces the current mode logic(CML) gate design method with which one can replace slow CMOS logic gates. The CML inverter exhibited small logic swing, fast response with high power consumption. But the power consumption became compatible with CMOS gates at higher clock speed. Due to small current values in CML, layout area is smaller than the CMOS counterpart even though CML uses larger number of devices. CML exhibited higher noise immunity thanks to its non-inverting and inverting outputs. Multi-input NAND/AND and NOR/OR gates were implemented by the same circuit architecture with different input confirugation. Same holds for MUX and XNOR/XOR CML gates. We concluded that the CML gates can be designed with few simple circuits and they can improve power consumption, chip area, and speed of operation.

• 한국정보디스플레이학회:학술대회논문집
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• 2007.08b
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• pp.1168-1171
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• 2007

Integrating systems on TFT-LCD panels is more and more popular for the mobile display application. However, it may not be necessary to use LTPS TFT devices. A-Si TFTs are used to integrate systems on TFT-LCD panels, especially scan (gate) drivers. To further reduce the chip size of driver IC, the triplegate pixel structure is developed. Therefore, the number of the source lines is reduced to 1/3 times.

• 한국정보디스플레이학회:학술대회논문집
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• 2007.08b
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• pp.1340-1343
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• 2007

We have simultaneously fabricated LTPS TFTs and integrated photodiodes on the same glass substrates without any additional LTPS process. The structure of an integrated photodiode is a lateral p-i-n diode with a gate. The performances of a photodiode were improved at a negative gate voltage.

• 한국정보디스플레이학회:학술대회논문집
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• 2005.07b
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• pp.1029-1032
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• 2005

A 262K-color QVGA LTPS AMLCD was developed. This panel has integrated gate driver and data multiplexer (1:3) by p_Si LTPS TFT process. The commercialized driver IC was adopted to implement this display. Fine image quality, low powerconsumption and cost-efficiency feature make the panel be suitable for mobile application.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.02a
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• pp.429-429
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• 2010

TFT 제조 방법 중 LTPS (Low Temperature Polycrystalline Silicon)는 저온과 저비용 등의 이점으로 인하여 flat panel display 제작에 널리 사용된다. 이동도와 전류 점멸비 등에서 이점을 가지는 ELA(Excimer Laser Annealing)가 널리 사용되고 있지만, 이 방법은 uniformity 등의 문제점을 가지고 있다. 이를 극복하기 위한 방법으로 MICC(Metal Induced Capping Crystallization)이 사용되고 있다. 이 방법은 $SiN_x$, $SiO_2$, SiON등의 capping layer를 diffusion barrier로 위치시키고, Ni 등의 금속을 capping layer에 도핑 한 뒤, 다시 한번 열처리를 통하여 a-Si에 Ni을 확산시키킨다. a-Si 층에 도달한 Ni들이 seed로 작용하여 Grain size가 매우 큰 film을 제작할 수 있다. 채널의 grain size가 클 경우 grain boundary에 의한 캐리어 scattering을 줄일 수 있기 때문에 MIC 방법을 사용하였음에도 ELA에 버금가는 소자의 성능과 안정성을 얻을 수있었다. 본 연구에서는 large grain TFT의 Gate bias stress에 따른 소자의 안정성 측정 및 분석에 목표를 두었다.