• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.06a
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• pp.246-247
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• 2007

최근 KEPRI-LSIS가 공동 개발한 하이브리드형 초전도 한류기 동작 시, 사고 검출을 담당하는 초전도체의 최적 설계에 적용하기 위하여 Au/YBCO 박막의 ��치 회복 특성을 조사하였다. $600\;V_{rms}$, 3 ms의 사고가 초전도 박막에 인가되었을 때, ��치가 종료된 이후 초전도성을 회복하기 위해 142 ms의 시간이 소요되었다. 또한 인가 시간이 증가함에 따라 소요 시간도 비례하여 증가하여 4 ms 동안 인가되었을 때, ��치 회복 시간은 272 ms로 측정되었다.

• Journal of Electrical Engineering and Technology
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• v.2 no.2
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• pp.263-266
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• 2007

We report a nickel optical MEMS switch, being able to rotate through a large angle and to accommodate multiple channels. The proposed optical switch consists of a thin nickel mirror and two torsion springs supporting the mirror. The torsion springs are designed using a finite element method (FEM) such that plastic deformation of the thin nickel is avoided during the large torsion actuation. For switching speed improvement, transient vibration of the released mirror is suppressed by optimizing the mirror design and a fast switching response of $200\;{\mu}s\;(pull-down)/300\;{\mu}s\;(pull-up)$ is demonstrated.

• Electrical & Electronic Materials
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• v.8 no.5
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• pp.648-657
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• 1995

정보처리의 다양화, 고속화를 위하여 장래의 집적회로는 다량의 정보를 단시간에 처리하지 않으면 안된다. 종래, 3년에 4배의 고집적화가 실현되어 LSI개발에 기술 견인차의 역할을 하고 있는 DRAM(Dynamic Random Access Memory)은 미세화기술의 한계를 우려하면서도 오히려 개발에 박차를 가하고 있다. 이러한 DRAM의 미세, 대용량화에는 미세가공 기술, 새로운 메모리 셀과 트랜지스터 기술, 새로운 회로 기술, 그 이외에 재료박막기술, Computer aided design/Design automation(CAD/DA) 기술, 검사평가기술 혹은 소형팩키지(package)기술등의 광범위한 기술발전이 뒷받침되어 왔다. 그 중에서 미세가공 기술 및 새로운 트랜지스터 기술과 메모리 셀 기술을 중심으로 개발 동향을 살펴보고 최근에 발표된 1Gbit DRAM의 시제품 기술에 대하여 분석해 보기로 한다.

• Proceedings of the Acoustical Society of Korea Conference
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• 1994.06a
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• pp.824-829
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• 1994

High-frequency and complex vibration ultrasonic wire bonding systems are propsed and their welding characteristic are studied. Ultrasonic wire bonding is used widely for joining thin connecting wire of various electronic devices including IC or LSI. Conventional bonding systems use vibration frequency of 40 or 60 kHz and linear vibration welding tips. Complex vibration welding tip which vibrates in elliptical to circular or rectangular to square in the same or different frequency is effective to join welding specimens in shorter welding time and under smaller vibration amplitude, and furthermore high-frequency systems such as 90, 120, 190 kHz are also significantly effective. High-frequency and complex vibration welding system of 90, 120 and 190 kHz are designed. Welding characteristics of these systems are found very superior than a conventional system. Welding specimens of aluminum wire of 0.1mm diameter are successfully.

• Journal of the Korea Society for Simulation
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• v.7 no.1
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• pp.15-26
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• 1998

In building a shell-based FMS, which is known as one of the top-down approaches in the field of factory automation, we may take a hybrid simulation into consideration. The modeling of a hybrid simulation consists of real physical entities, virtual simulation, and central clock algorithm, etc. to carry out the whole system operation. In this paper, we sow a way to construct a hybrid simulation software system in manufacturing environments. We bring in the object-oriented methodology in system design and it can contribute in dealing with a wide variety of production types and configurations. Some classes such as project, product, process, order, schedule, stage are defined. These are used and tested by implementing a specific LSI circuit assembly line process.

• Journal of Multimedia Information System
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• v.5 no.4
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• pp.273-276
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• 2018

In video compression standards, the entropy coding is essential to the high performance compression because redundancy of data symbols is removed. Binary arithmetic coding is one of high performance entropy coding methods. However, the dependency between consecutive binary symbols prevents improving the throughput. For the throughput enhancement, a new probability model is proposed for encoding multi-symbols at one time. In the proposed method, multi-symbol encoder is implemented with only adders and shifters, and the multiplication table for interval subdivision of binary arithmetic coding is removed. Compared to the compression ratio of CABAC of H.264/AVC, the performance degradation on average is only 1.4% which is negligible.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.23 no.12
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• pp.1734-1737
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• 2019

This paper presents a prediction structure with a Hybrid Dynamic Branch Prediction (HDBP) scheme which decreases the number of stalls. In the application, a branch history register is dynamically adjusted to produce more unique index values of pattern history table (PHT). The number of stalls is also reduced by using the modified gshare predictor with a long history register folding scheme. The aliasing rate decreased to 44.1% and the miss prediction rate decreased to 19.06% on average compared with the gshare branch predictor, one of the most popular two-level branch predictors. Moreover, Compared with the gshare, an average improvement of 1.28% instructions per cycle (IPC) was achieved. Thus, with regard to the accuracy of branch prediction, the HDBP is remarkably useful in boosting the overall performance of the superscalar processor.

• Journal of the Korean Institute of Telematics and Electronics
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• v.23 no.6
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• pp.981-987
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• 1986

This paper describes the CIREX(CIRcuit EXtractor), an automated CMOS circuit extraction program which provides SPICE2 input file by computing circuit connectivity and transistor dimensions from the CIF file. The CIREX also computes parasitic capacitance and resistance which makes it a valuable tool for timing analysis and detailed circuit simulation. A lattice model is used to calculate the interconnection resistances and substrate capacitances which can be replaced, as an option, by a node model for the worst case timing analysis of the circuit.

• Journal of the Korean Institute of Telematics and Electronics
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• v.23 no.6
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• pp.741-746
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• 1986

A novel n-p-n bipolar transistor of which emitter is self-aligned with base contact by polyilicon is developed for using in high speed and high packing density LSI circuits. The emitter of this transistor is separated less than 0.4 \ulcorner with base contact by self-aligh technology, and the emitter feature size is less than 3x5 \ulcorner\ulcorner Because the active region of this transistor is not damaged through all the process, it has excellent electric properties. Using the n-p-n transistors by 3.0\ulcorner design rules, a NTL ring oscillator has 380 ps, a CML ring oscillator has 390ps, and a I\ulcorner ring oscillator has 5.6ns of per-gate minimum propagation delay time.

• Journal of the Korean Institute of Telematics and Electronics
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• v.23 no.4
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• pp.550-556
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• 1986

This paper proposes a two-layer channel routing algorithm using the division of signal nets in LSI/VLSI layout design. To solve the vertical constraint problem, the doglegging method is used. Although signal net division and the dogleg are used, the routing is accomplished within local channel density and the increase in vias is repressed by assining the vertical segments to the metal layer and the horizontal segments to the poly layer. The algorithm was implemented on a VAX 11/780 computer. The effectiveness of the proposed algorithm is proved by appling this algorithm to Deutch's difficult example.