• 한국초지조사료학회지
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• 제43권3호
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• pp.168-176
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• 2023

Silicon (Si) has the potential to improve plant growth and stress tolerance. The study aimed to explore Si-involving plant responses and molecular characterization of different Si-responsive genes in alfalfa. In this study, the exogenous supplementation of Si enhanced plant growth, and biomass yield. Si-acquisition in alfalfa root and shoot was higher in Si-supplemented compared to silicon deficient (-Si) plants, implying Si-acquisition has beneficial on alfalfa plants. As a consequence, the quantum efficiency of photosystem II (Fv/Fm) was significantly increased in silicon-sufficient (+Si) plants. The quantitative gene expression analysis exhibited a significant upregulation of the Lsi1, Lsi2, Lsi3, NIP5;1, and NIP6;1 genes in alfalfa roots, while BOR1, BOR4, NIP2, and NIP3 showed no significant variation in their expression. The MEME results further noticed the association of four motifs related to the major intrinsic protein (MIP). The interaction analysis revealed that NIP5;1 and Lsi1 showed a shared gene network with NIP2, BOR1, and BOR4, and Lsi2, Lsi3 and NIP3-1, respectively. These results suggest that members of the major intrinsic proteins (MIPs) family especially Lsi1, Lsi2, Lsi3, NIP5;1, and NIP6;1 genes helped to pass water and other neutral solutes through the cell membrane and those played significant roles in Si uptake and transport in plants. Together, these insights might be useful for alfalfa breeding and genome editing approaches for alfalfa improvement.

• JSTS:Journal of Semiconductor Technology and Science
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• 제5권4호
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• pp.221-228
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• 2005

In this work, our goal is to develop a fast and accurate power model of the ARM926EJ-S processor in the industrial design environment. Compared with existing work on processor power modeling which focuses on the power states of processor core, our model mostly focuses on the cache power model. It gives more than 93% accuracy and 1600 times speedup compared with post-layout gate-level power estimation. We also address two practical issues in applying the processor power model to the real design environment. One is to incorporate the power model into an existing commercial instruction set simulator. The other is the re-characterization of power model parameters to cope with different gate-level netlists of the processor obtained from different design teams and different fabrication technology.

• JSTS:Journal of Semiconductor Technology and Science
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• 제5권4호
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• pp.229-236
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• 2005

This paper presents a system level architecture evaluation technique that leverages transaction level modeling but also significantly extends it to the realm of system level performance evaluation. A major issue lies with the modeling effort. To reduce the modeling effort the proposed technique develops the concept of worst case scenarios. Since the memory controller is often found to be an important component that critically affects the system performance and thus needs optimization, the paper further addresses how to evaluate and optimize the memory controllers, focusing on the test environment and the methodology. The paper also presents an industrial case study using a real state-of-the-art design. In the case study, it is reported that the proposed technique has helped successfully find the performance bottleneck and provide appropriate feedback on time.

• 한국지능시스템학회논문지
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• 제17권4호
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• pp.569-574
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• 2007

최근 많은 광대역 유무선 통신 응용분야에서 OFDM(Orthogonal Frequency Division Multiplexing) 방식을 표준기술로 채택하고 있다. OFDM 방식의 고속 무선 데이터 통신을 위한 FFT 프로세서는 일반적으로 DSP(Digital Signal Processing)로 구현되었으나, 큰 전력 소비를 필요로 한다. 따라서, OFDM 통신방식의 단점인 전력문제를 보완하기 위해서 전류모드 FFT LSI가 제안되었고, 저소비전력 전류모드 FFT LSI를 동작시키기 위해서는 전류모드를 전압모드로 바꾸는 VIC(Voltage to Current Converter) 그리고 다시 전류모드를 전압모드로 바꾸어 주는 IVC(Current to Voltage Converter)가 필요하다. 그러나, OP-AMP로 구현되는 종래의 IVC는 회로규모가 크고, 전력소비가 크며, LSI 내에 크고 정확한 높은 저항을 필요로 한다. 또한 전류모드신호처리에서 많이 이용되는 Current Mirror 회로 등의 출력단자로부터 전류신호를 입력받은 경우, 입력단자간의 전위차가 발생하며, DC offset 전류가 발생하는 등의 문제점을 갖는다. 따라서 본 연구에서는 저전력 동작이 가능하고, 향후, single chip 응용이 가능한 IVC를 $0.35{\mu}m$ 공정에서 설계함으로서, $0.35{\mu}m$ 공정에서의 전류모드 FFT LSI의 전압모드 출력이 가능해졌다 설계된 IVC는 FFT LSI의 출력이 디지털신호로 환산한 ${\pm}1$인 점을 감안하여, 전류모드 FFT LSI의 출력이 $13.65{\mu}A$ 이상일 때에 3.0V의 전압을 출력하고, FFT LSI의 출력이 $0.15{\mu}A$ 이하일 때에 0.5V 이하의 전압을 출력하도록 하였으며, IVC의 총 소비전력은 약 1.65mV이하로 평가되었다.

• Journal of Preventive Medicine and Public Health
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• 제30권2호
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• pp.392-401
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• 1997

Generally working environment and worker's health status of small scale industries (SSI) which employ less than 50 workers are known to be poorer than those of large scale industries(LSI) which employ more than 500 workers. However, according to the analysis of occupational injuries in Korea, prevalence rate of occupational injuries of SSI was 3.1 times as high as LSI. But there was no difference in prevalence rate of occupational disease and werkers with suspected occupational disease(D1) between SSI and LSI. To confirm these two different facts, we surveyed working environment and worker's health status of SSI and LSI in Kyeungin industrial complex. Workers in SSI were 10,878 and workers in LSI were 8,291 and number of hazardous agents in SSI were 3,554 and those of LSI were 1,916. We found following results. First, proportion of male workers and workers who were less than 30 yens old and more than 50 yens old was higher in SSI compared to LSI. Second, worker in SSI had more liver disease, viral hepatitis, and pneumoconiosis than in LSI, and there were more worker with suspected occupational disease, general disease, and worker needed close observation in SSI. But these effects had not statistical significance under the condition controlled by age and sex with logistic regression. Third, the numbers measured for specific chemicals, organic solvents, and heavy metals in SSI was more than in LSI. However there was on difference in the excess rate of each hazardous agent between SSI and LSI. As the above results workers' health status in SSI was poorer than in LSI, but these results were mainly due to the population structure difference. Although there were some limitation of this study and problems of sensitivity and validity for periodic health examination and working environment evaluation method, the concept that working environment and worker's health status in SSI should be reviewed. In future the study that will reveal the real weak point of SSI should be performed.

• ETRI Journal
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• 제7권2호
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• pp.43-48
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• 1985

일반적으로 시분할 전자 교환기의 time-switch로는 RAM을 이용한 방식이 많이 사용되고 있는데 본고에서는 간단한 하드웨어와 빠른 교환 속도의 특징을 갖는 고속 디지틀 스위칭 IC, HDS(Highspeed Digital Switch)-LSI에 관하여 간단히 소개하고자 한다. 먼저 일반적인 time-switch의 구조와 동작에 대해 간단히 설명하고 HDS-LSI의 기본 원리와 구조 그리고 응용 분야에 대해 예를들어 설명하였다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1987년도 전기.전자공학 학술대회 논문집(II)
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• pp.1305-1308
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• 1987

This paper presents a design of an optimized implantable biotelemetry system and the fabrication of custom CMOS LSI for implementing this system. The internal circuits of this system are fabricated on a single silicon chip with a size of $4{\times}5mm^2$. This LSI is designed and fabricated not only to get as small size and low power dissipation as possible, but also to have multiple function. Its main functions are to select one of implanted sensors and to accomplish ON - OFF power switching of an implanted battery by receiving appropriate Command signals and control signals fran external circuits. The internal system which was assembled on a bread-board using fabricated LSI chip is confirmed to work as designed. The total power dissipation of this interal system was $10.12{\mu}W$.

• ETRI Journal
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• 제25권5호
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• pp.288-296
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• 2003

In this study, we present a 260k color TFT LCD driver chip set that consumes only 5 mW in the module, which has exceptionally low power consumption. To reduce power consumption, we used many power-lowering schemes in the logic and analog design. A driver IC for LCDs has a built-in graphic SRAM. Besides write and read operations, the graphic SRAM has a scan operation that is similar to the read operation of one row-line, which is displayed on one line in an LCD panel. Currently, the embedded graphic memory is implemented by an 8-transistor leaf cell and a 6-transistor leaf cell. We propose an efficient scan method for a 6-transistor embedded graphic memory that is greatly improved over previous methods. The proposed method is implemented in a 0.22 ${\mu}m$ process. We demonstrate the efficacy of the proposed method by measuring and comparing the current consumption of chips with and without our proposed scheme.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 ITC-CSCC -3
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• pp.1559-1562
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• 2002

This paper describes a 0.13um ultra-high speed 1Mb CMOS SRAM macro with 1.7ns access time. It achieves ultra-high speed operation using two novel approaches. First, it uses process insensitive sense amplifier (Double-Equalized Sense Amplifier) which improves voltage offset by about 10 percent. Secondly, it uses new replica-based sense amplifier driver which improves bit- line evaluation time by about 10 percent compared to the conventional technique. The various memory macros can be generated automatically by using a compiler, word-bit size from 64kb to 1 Mb including repairable redundancy circuits.

• 제어로봇시스템학회논문지
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• 제4권3호
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• pp.329-333
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• 1998

본 논문에서는, LSI 적층 기술을 이용한 실시간 처리 마이크로 비젼의 개발을 소개하고 있다. 새롭게 개발된 LSI 적층기술을 이용하여, 영상신호의 증폭, 변환, 연산처리등의 기본기능을 가지는 다수의 LSI 웨이퍼를 적층한다. 각 층간의 고밀도 수직배선을 통하여 대량의 영상정보를 동시에 전달하므로써, 대규모 동시 병렬처리를 가능하게 하며, 다수의 층에 걸쳐 파이프 라인 처리가 이루어진다. VLSI 설계시스템을 이용하여, 윤곽 검출기능을 가지는 테스트 칩을 설계(2 .mu.m CMOS design rule)하고, 시뮬레이션을 통하여 양호한 동작(처리시간 10 .mu.s)을 확인하고 있다. 시험제작을 위해서는, 새롭게 개발된 LSI 적층기술이 이용된다. 영상처리의 기본회로가 실려있는 웨이퍼의 기반을 30 .mu.m 의 두께까지 연마하고, 개발된 웨이퍼 aligner를 이용하여 수직배선이 형성된 상하 두 개의 웨이퍼를 미세조정하면서 접착한다. 이상의 제작과정을 반복하여 두께 1mm이하의 인공망막과 같은 마이크로 비젼을 제작한다.