• Journal of the Korean Society of Propulsion Engineers
• /
• v.16 no.2
• /
• pp.25-33
• /
• 2012

A genetic algorithm (GA) has been employed to optimize the major design variables of the liquid rocket engine. Pressure of the main combustion chamber, nozzle expansion ratio and O/F ratio have been selected as design variables. The target engine has the open gas generator cycle using the LO2/RP-1 propellant. The gas properties of the combustion chamber have been obtained from CEA2 and the mass has been estimated using reference data. The objective function has been set as multi-objective function with the specific impulse and thrust to weight ratio using the weight method. The result shows about 4% improvement of the specific impulse and 23% increase of the thrust to weight ratio. The Pareto frontier line has been also obtained for various thrust requirements.

• Proceedings of the Korean Society of Propulsion Engineers Conference
• /
• 2011.11a
• /
• pp.127-134
• /
• 2011

A genetic algorithm (GA) has been employed to optimize the major design variables of the liquid rocket engine. Pressure of the main combustion chamber, nozzle expansion ratio and O/F ratio have been selected as design variables. The target engine has the open gas generator cycle using the LO2/RP-1 propellant. The gas properties of the combustion chamber have been obtained from CEA2 and the mass has been estimated using reference data. The objective function has been set as multi-objective function with the specific impulse and thrust to weight ratio using the weight method. The result shows about 4% improvement of the specific impulse and 23% increase of the thrust to weight ratio. The Pareto frontier line has been also obtained for various thrust requirements.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.46 no.8
• /
• pp.117-124
• /
• 2009

This paper describes a 3 to 5 GHz frequency synthesizer for MB-OFDM (Multi-Band OFDM) UWB (Ultra- Wideband) application using 0.13 ${\mu}m$ CMOS process. The frequency synthesizer operates in the band group 1 whose center frequencies are 3432 MHz 3960 MHz, and 4488 MHz. To cover the overall frequencies of group 1, an efficient frequency planning minimizing a number of blocks and the power consumption are proposed. And, a high-frequency VCO and LO Mixer architecture are also presented in this paper. A new mixed coarse tuning scheme that utilizes the MIM capacitance, the varactor arrays, and the DAC is proposed to expand the VCO tuning range. The frequency synthesizer can also provide the clock for the ADC in baseband modem. So, the PLL for the ADC in the baseband modem can be removed with this frequency synthesizer. The single PLL and two SSB-mixers consume 60 mW from a 1.2 sV supply. The VCO tuning range is 1.2 GHz. The simulated phase noise of the VCO is -112 dBc/Hz at 1 MHz offset. The die area is 2 ${\times}$ 2mm$^2$.

• Journal of IKEEE
• /
• v.25 no.4
• /
• pp.721-727
• /
• 2021

This paper proposes a UWB (Ultar-wideband) impulse generator using the gated ring oscillator. The oscillator and PLL circuits which generate a several GHz LO signal for the conventional architecture are replaced with the gated ring oscillator. Therefore, the system complexity is decreased. The proposed architecture controls the duty of enable signal, which is used for the head switch of ring oscillator. The control of the duty enables to tun off the oscillator during the guard interval and stop wasting the power consumption. The pulse shaping method using the counter makes the small side lobe and preserves the bandwidth regardless of the change on the center frequency. Designed UWB impulse generator could change the center frequency from 6.0 GHz to 8.8 GHz with a digital bit control, while it preserves the bandwidth as about 1.5 GHz.

• ETRI Journal
• /
• v.26 no.3
• /
• pp.229-240
• /
• 2004

This paper reports on our development of a dual-mode transceiver for a CMOS high-rate Bluetooth system-onchip solution. The transceiver includes most of the radio building blocks such as an active complex filter, a Gaussian frequency shift keying (GFSK) demodulator, a variable gain amplifier (VGA), a dc offset cancellation circuit, a quadrature local oscillator (LO) generator, and an RF front-end. It is designed for both the normal-rate Bluetooth with an instantaneous bit rate of 1 Mb/s and the high-rate Bluetooth of up to 12 Mb/s. The receiver employs a dualconversion combined with a baseband dual-path architecture for resolving many problems such as flicker noise, dc offset, and power consumption of the dual-mode system. The transceiver requires none of the external image-rejection and intermediate frequency (IF) channel filters by using an LO of 1.6 GHz and the fifth order onchip filters. The chip is fabricated on a $6.5-mm^{2}$ die using a standard $0.25-{\mu}m$ CMOS technology. Experimental results show an in-band image-rejection ratio of 40 dB, an IIP3 of -5 dBm, and a sensitivity of -77 dBm for the Bluetooth mode when the losses from the external components are compensated. It consumes 42 mA in receive ${\pi}/4-diffrential$ quadrature phase-shift keying $({\pi}/4-DQPSK)$ mode of 8 Mb/s, 35 mA in receive GFSK mode of 1 Mb/s, and 32 mA in transmit mode from a 2.5-V supply. These results indicate that the architecture and circuits are adaptable to the implementation of a low-cost, multi-mode, high-speed wireless personal area network.

• Journal of Digital Contents Society
• /
• v.10 no.4
• /
• pp.625-632
• /
• 2009

In these days mobile handsets have come to be used at almost every user. The performance improvement of mobile devices and networks have made this trend possible. As a great variety of mobile applications are published, the necessity of running large-scale mobile applications becomes greater than before. To accomplish this, the existing researchers have developed mobile cluster computing libraries like Mobile-JPVM. In this paper, we implement a compute-intensive Animated GIF generating application and its cell phone viewer software using Mobile-JPVM library. We find out by the real execution of our softwares on the KTF handsets that they can sufficiently run on cellular phones. Our Animated GIF generator and its viewer are going to be commercially used for the mobile fashion advertisement systems.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.16 no.1
• /
• pp.126-142
• /
• 2016

This paper presents a wide-frequency-range, low-power transceiver with an automatic impedance-matching calibration for TV-white-space (TVWS) application. The wide-range automatic impedance matching calibration (AIMC) is proposed for the Drive Amplifier (DA) and LNA. The optimal $S_{22}$ and $S_{11}$ matching capacitances are selected in the DA and LNA, respectively. Also, the Single Pole Double Throw (SPDT) switch is integrated to share the antenna and matching network between the transmitter and receiver, thereby minimizing the systemic cost. An N-path filter is proposed to reject the large interferers in the TVWS frequency band. The current-driven mixer with a 25% duty LO generator is designed to achieve the high-gain and low-noise figures; also, the frequency synthesizer is designed to generate the wide-range LO signals, and it is used to implement the FSK modulation with a programmable loop bandwidth for multi-rate communication. The TVWS transceiver is implemented in $0.13{\mu}m$, 1-poly, 6-metal CMOS technology. The die area of the transceiver is $4mm{\times}3mm$. The power consumption levels of the transmitter and receiver are 64.35 mW and 39.8 mW, respectively, when the output-power level of the transmitter is +10 dBm at a supply voltage of 3.3 V. The phase noise of the PLL output at Band 2 is -128.3 dBc/Hz with a 1 MHz offset.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.21 no.6
• /
• pp.670-680
• /
• 2010

A low power single-chip CMOS receiver for 60 GHz mobile application are proposed in this paper. The single-chip receiver consists of a 4-stage current re-use LNA with under 4 dB NF, Cgs compensating resistive mixer with -9.4 dB conversion gain, Ka-band low phase noise VCO with -113 dBc/Hz phase noise at 1 MHz offset from 26.89 GHz, high-suppression frequency doubler with -0.45 dB conversion gain, and 2-stage current re-use drive amplifier. The size of the fabricated receiver using a standard 0.13 ${\mu}m$ CMOS technology is 2.67 mm$\times$0.75 mm including probing pads. An RF bandwidth is 6.2 GHz, from 55 to 61.2 GHz and an LO tuning range is 7.14 GHz, from 48.45 GHz to 55.59 GHz. The If bandwidth is 5.25 GHz(4.75~10 GHz) The conversion gain and input P1 dB are -9.5 dB and -12.5 dBm, respectively, at RF frequency of 59 GHz. The proposed single-chip receiver describes very good noise performances and linearity with very low DC power consumption of only 21.9 mW.