• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.6
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• pp.1355-1362
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• 2011

This paper describes a multi-mode LDPC decoder which supports three block lengths(648, 1296, 1944) and four code rates(1/2, 2/3, 3/4, 5/6) of IEEE 802.11n WLAN standard. Our LDPC decoder adopts a block-serial architecture based on min-sum algorithm and layered decoding scheme. A novel way to store check-node values and parity check matrix reduces the sizes of check-node memory and H-ROM. An efficient scheme for check-node memory addressing is used to achieve stall-free read/write operations. The designed LDPC decoder is verified by FPGA implementation, and synthesized with a $0.18-{\mu}m$ CMOS cell library. It has 219,100 gates and 45,036 bits RAM, and the estimated throughput is about 164~212 Mbps at 50 MHz@2.5v.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.9C
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• pp.801-809
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• 2007

LDPC Low Density Parity Check) code, which is an error correcting code determined to be applied to the 4th generation mobile communication systems, requires a heavy computational complexity due to iterative decodings to achieve a high BER performance. This paper proposes an algorithm to reduce the number of decoding iterations to increase performance of the decoder in decoding latency and power consumption. Measuring changes between the current decoded LLR values and previous ones, the proposed algorithm predicts directions of the value changes. Based on the prediction, the algorithm inverts the sign bits of the LLR values to speed up convergence, which means parity check equation is satisfied. Simulation results show that the number of iterations has been reduced by about 33% without BER performance degradation in the proposed decoder, and the power consumption has also been decreased in proportional to the amount of the reduced decoding iterations.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.5C
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• pp.432-438
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• 2010

In this paper we study the effect of bit-to-symbol mappings on the convergence behavior of turbo equalizers employing low-density parity-check (LDPC) codes over high order modulations. We analyze the effective SNR of the outputs from linear minimum mean-squared error (MMSE) equalizers and the convergence property of LDPC decoding for different symbol mappings. Numerical results show that the bit-reliability (BR) mapping provides better performance than random mapping in LDPC-coded turbo equalizers over high order modulations. We also verify the effect of symbol mappings through the noise threshold and error performance.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.12
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• pp.2791-2797
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• 2010

In recent years, the goal of providing high speed wireless data services has generated a great amount of interest among the research community. Several researchers have shown that the capacity of the system, in the presence of flat Rayleigh fading, improves significantly with the use of combined MIMO and LDPC. To feed the soft values to LDPC decoder, the soft values must be calculated from multiple transmitter and receiver antennas in Rayleigh fading channel. It requires high computational complexity to get the soft symbols by increasing number of transmitter and receiver antennas. Therefore, this thesis proposed on effective algorithm for calculation of soft values from multiple antennas based on LLR. As result, This thesis shows that maximum 61% of computational complexity is reduced with a little loss of performance.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.1C
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• pp.20-25
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• 2006

In this paper, the performance of Tree-LDPC code is presented based on the min-sum algorithm with scaling and the asymptotic performance in the water fall region is shown by density evolution. We presents that the Tree-LDPC code show a significant performance gain by scaling with the optimal scaling factor which is obtained by density evolution methods. We also show that the performance of min-sum with scaling is as good as the performance of sum-product while the decoding complexity of min-sum algorithm is much lower than that of sum-product algorithm. The Tree-LDPC decoder is implemented on a FPGA chip with a small interleaver size.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2010.05a
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• pp.486-489
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• 2010

This paper describes a layered LDPC decoder which supports block length of 1,944 bits and code rate 1/2 for IEEE 802.11n WLAN standard. To reduce the hardware complexity, the min-sum algorithm and layered architecture is adopted. A novel memory reduction technique suitable for min-sum algorithm reduces memory size by 75% compared with conventional method. The designed processor has 200,400 gates and 19,400 bits memory, and it is verified by FPGA implementation. The estimated throughput is about 200 Mbps at 120 MHz clock by using Xilinx Virtex-4 FPGA device.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2013.10a
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• pp.399-401
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• 2013

In this paper, we present the method to impove the performance by using iterative decoding in LDPC codes with 8-PSK modulation. Iterative decoding is the technique that improve the performance after the input signals of receiver are re-calculated by using the soft decision output of decoder. DVB-S2 system with 8-PSK modulation based on iterative decoding had a better performance than DVB-S2 with 8-PSK modulation over Gaussian channels.

• Proceedings of the KIEE Conference
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• 2006.07d
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• pp.2027-2028
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• 2006

추정된 채널 정보를 바탕으로 적용하는 적응형 비트 로딩 방식은, 전력선 통신 시스템의 고속화 및 대용량 데이터 전송을 위해 최근 대두되고 있는 LDPC(Low Density Parity Check) coded OFDM 시스템에 대해, 한정된 주파수 대역과 신호 전력의 효율적 사용을 제공한다. 그러나 적응형 비트로딩 방식은 한정된 수의 일정 SNR(신호대 잡음 전력비) 구간에 대한 mapping 방식으로 적용되기 때문에 송수신 과정에서 추정된 채널 정보를 이용하는 sum-product 복호기가 채널 변화에 민감하게 반응하지 못하는 상황이 발생하며, 결국 송신단에서 채널 추정 결과를 바탕으로 선택된 SNR 범위에 대해서는 실제 수신되는 신호에 대한 SNR과의 차이가 존재하고 시스템의 성능은 그 만큼의 성능 열하로 나타나게 된다. 본 논문에서는 이러한 성능 열하 정도를 시뮬레이션을 통해 확인하였다.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.1
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• pp.189-195
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• 2008

The OFDMA Physical layer in the WiMAX standard of IEEE 802.16e adopts 114 LDPC codes with various code rates and block sizes as a channel coding scheme to meet varying channel environments and different requirements for transmission performance. In this paper, the performances of the LDPC codes are evaluated according to various code rates and block-lengths throueh simulation studies using min-sum decoding algorithm in AWGN chamois. As the block-length increases and the code rate decreases, the BER performance improves. In the cases with code rates of 2/3 and 3/4, where two different codes ate specified for each code rate, the codes with code rates of 2/3A and 3/4B outperform those of 2/3B and 3/4A, respectively. Through the statistical analyses of the number of decoding iterations the decoding complexity and the word error rates of LDPC codes are estimated. The results can be used to trade-off between the performance and the complexity in designs of LDPC decoders.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.6
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• pp.1323-1329
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• 2014

In this paper, we analyzed efficient decoding scheme with FTN (Faster than Nyquist) method that is transmission method faster than Nyquist theory and increase the throughput. we proposed viterbi equalizer model to minimize ISI (Inter-Symbol Interference) when FTN signal is transmitted. the proposed model utilized interference as branch information. In this paper, to decode FTN singal, we used turbo equalization algorithms that iteratively exchange probabilistic information between soft Viterbi equalizer (BCJR method) and LDPC decoder. By changing the trellis diagram in order to maximize Euclidean distance, we confirmed that performance was improved compared to conventional methods as increasing throughput of FTN signal.