• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.38B no.2
• /
• pp.140-145
• /
• 2013

This paper proposes the high speed LDPC decoder structure base on the DVB-S2. Firstly, We study the solution to avoid the memory conflict. For the high speed decoding process the decoder adapts the HSS(Horizontal Shuffle Scheduling) scheme. Secondly, for the high speed decoding algorithm normalized Min-Sum algorithm is adapted instead of Sum-Product algorithm. And the self corrected is a variant of the LDPC decoding that sets the reliability of a Mc${\rightarrow}$v message to 0 if there is an inconsistency between the signs of the current incoming messages Mv'${\rightarrow}$c and the sign of the previous incoming messages Moldv'${\rightarrow}$c This self-corrected algorithm avoids the propagation on unreliable information in the Tanner graph and thus, helps the convergence of the decoder.Start after striking space key 2 times. Lastly, and this paper propose the optimal hardware architecture supporting the high speed throughput.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.17 no.2
• /
• pp.363-371
• /
• 2013

This paper describes a multi-standard LDPC decoder which supports 19 block lengths(576~2304) and 6 code rates(1/2, 2/3A, 2/3B, 3/4A, 3/4B, 5/6) of IEEE 802.16e mobile WiMAX standard and 3 block lengths(648, 1296, 1944) and 4 code rates(1/2, 2/3, 3/4, 5/6) of IEEE 802.11n WLAN standard. To minimize hardware complexity, it adopts a block-serial (partially parallel) architecture based on the layered decoding scheme. A DFU(decoding function unit) based on sign-magnitude arithmetic is used for hardware reduction. The designed LDPC decoder is verified by FPGA implementation, and synthesized with a 0.13-${\mu}m$ CMOS cell library. It has 312,000 gates and 70,000 bits RAM. The estimated throughput is about 79~210 Mbps at 100 MHz@1.8v.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2011.05a
• /
• pp.132-135
• /
• 2011

This paper describes a multi-mode LDPC decoder which supports three block lengths(648, 1296, 1944) and four code rates(1/2, 2/3, 3/4, 5/6) of IEEE 802.11n WLAN standard. To minimize hardware complexity, it adopts a block-serial (partially parallel) architecture based on the layered decoding scheme. A novel memory reduction technique devised using the min-sum decoding algorithm reduces the size of check-node memory by 47% as compared to conventional method. The designed LDPC decoder is verified by FPGA implementation, and synthesized with a $0.18-{\mu}m$ CMOS cell library. It has 219,100 gates and 45,036 bits RAM, and the estimated throughput is about 164~212 Mbps at 50 MHz@2.5v.

• Proceedings of the Korean Society of Broadcast Engineers Conference
• /
• 2015.07a
• /
• pp.301-302
• /
• 2015

케이블 방송망에서 멀티-Gbps(Giga bit per second) 초고속 인터넷 서비스 제공을 위해 최근 북미에서 DOCSIS 3.1(Data over Cable Service Interface Specifications Version 3.1) 표준을 발표하였다. DOCSIS 3.1 은 최대 10Gbps 하향 데이터 전송과 최대 2Gbps 의 상향 데이터 전송을 목표로 한다. DOCSIS 3.1 이 이전 DOCSIS 표준들과 다른 점은 전송 효율을 높이기 위해 물리계층 전송 방식에 큰 변화를 주었다는 점이다. 기존 6MHz 대역폭의 단일 반송파 전송 방식에서 최대 192MHz 광역 채널의 다중 반송파 전송 방식으로 변경하였다. 또한 채널 오류정정 방식으로 BCH(Bose, Chaudhuri, and Hocquenghem)와 LDPC(Low Density Parity Check) 연접부호를 적용하여, 이로 인한 SNR 성능 이득 통해 4096-QAM 의 고차 변조를 지원한다. 본 논문에서는 최대 192MHz 의 광역 채널로 전송되는 약 2Gbps 의 전송 데이터에 대한 채널 오류 정정을 위해 고속의 LDPC 복호기 구현 방법을 제시한다.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.53 no.12
• /
• pp.36-41
• /
• 2016

LDPC code has beend applied in recent communication standards, such as Wi-Fi, WiGig, 10GBased-T Ethernet as a forward error correction code. However, LDPC code is required a large amount of computational complexity due to large iterations and block lengths for high performances. To solve this problem, various research has been continously performed for reducing computational complexity. In this paper, we propose AFC algorithm to deactive the variable and check node for reduce the computational complexity.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.13 no.10
• /
• pp.2227-2234
• /
• 2009

DVB-SSP is a new broadcasting system for hybrid satellite communications, which supports mobile handheld systems and fixed terrestrial systems. An upper layer, including erasure Reed-Solomon error correction combined with cyclic redundancy check. However, a critical factor must be considered in upper layer decoding. If there is only one bit error in an IP packet, the entire IP packet is considered as unreliable bytes, even if it contains correct bytes. If, for example, there is one real byte error, in an IP packet of 512 bytes, 511 correct bytes are erased from the frame. Therefore, this paper proposed upper layer decoding methods; LLR-based decoding. By means of simulation we show that the performance of the proposed decoding algorithm is superior to that of the conventional one.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.36 no.6C
• /
• pp.368-375
• /
• 2011

In the distributed video coding system, the parity bits, which are generated in encoders, are used to reconstruct Wyner-Ziv frames. Since the original Wyner-Ziv frames are not known in decoders, the efficient correlation noise modeling for turbo or LDPC code is necessary. In this paper, an efficient correlation noise modeling method is proposed and the performance is analyzed. The method to estimate the quantization parameters for key frames, which are encoded using H.264 intraframe coding technique, is also proposed. The performance of the proposed system is evaluated by extensive computer simulations.

• Proceedings of the IEEK Conference
• /
• 2004.06a
• /
• pp.51-54
• /
• 2004

In this paper, we analyze the performance of LDPC decoder for DVB-S2 system. The performance analysis is performed by computer simulations based on AWGN channel and high order modulation technique including 16APSK and 32APSK. For normal frame codeword length N = 64800, the performance of LDPC decoder is only away 0.7dB to 1dB from Shannon limit with respect to each modulation. The constructions and encoding process of LDPC codes which are used for DVB-S2 system are also presented and described.

• IEMEK Journal of Embedded Systems and Applications
• /
• v.4 no.4
• /
• pp.195-200
• /
• 2009

As 4G mobile communication systems require high transmission rates with reliability, the need for efficient error correcting code is increasing. In this paper, a novel LDPC (Low Density Parity Check) decoder is introduced. The LDPC code is one of the most popular error correcting codes. In order to improve performance of the LDPC decoder, we use SNR (Signal-to-Noise Ratio) estimation results to adjust coefficients of modified UMP-BP (Uniformly Most Probable Belief Propagation) algorithm which is one of widely-used LDPC decoding algorithms. An advantage of Modified UMP-BP is that it is amenable to implement in hardware. We generate the optimal values by simulation for various SNRs and coefficients, and the values are stored in a look-up table. The proposed decoder decides coefficients of the modified UMP-BP based on SNR information. The simulation results show that the BER (Bit Error Rate) performance of the proposed LDPC decoder is better than an LDPC decoder using a conventional modified UMP-BP.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.28 no.5C
• /
• pp.532-538
• /
• 2003

In this paper we have investigated a novel approach applying low-density parity-check coding to a COFDM-CDMA system, which operates in a multi-path fading mobile channel. Developed as a linear-block channel coder, the LDPC code is known for a superior signal reception capability in AWGN and/or flat fading channels with respect to increased encoding rates, however, its performance degrades when the communication channel becomes multi-path fading. For a typical multi-path fading mobile channel with a SNR of 16㏈ or lower. in order to obtain a BER lower than 1 out of 10000, the LDPC code with encoding rates below 1:3 requires not only the inherent parity check information but also the piloting information for refreshing front-end equalizer taps of COFDM-CDMA, periodically. For instance, while the 1:3-rate LDPC coded transmission symbol is consisted of data bits and parity-check bits in 1 to 3 proportion, on the other hand, in the proposed method the same rate LDPC transmission symbol contains data bits, parity check bits, and pilot bits in 1 to 2 to 1 proportion, respectively. The included pilot bits are effective not only for channel estimation and channel equalization but for symbol decoding by assisting the parity-check bits, hence, improving SNR vs BER performance over the conventional 1:3-rate LDPC code. The proposed system performance has been verified using computer simulations in multi-path, Rayleigh fading channels, and the results show us that the proposed method out-performs the general LDPC channel coding methods in terms of SNR vs BER measurements.