• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.4
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• pp.921-929
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• 2011

This paper describes an analysis of the decoding performance and decoding convergence speed of layered LDPC(low-density parity-check) decoder for mobile WiMAX system, and the optimal design conditions for hardware implementation are searched. A fixed-point model of LDPC decoder, which is based on the min-sum algorithm and layered decoding scheme, is implemented and simulated using Matlab model. Through fixed-point simulations for the block lengths of 576, 1440, 2304 bits and the code rates of 1/2, 2/3A, 2/3B, 3/4A, 3/4B, 5/6 specified in the IEEE 802.16e standard, the effect of internal bit-width, block length and code rate on the decoding performance are analyzed. Simulation results show that fixed-point bit-width larger than 8 bits with integer part of 5 bits should be used for acceptable decoding performance.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.48 no.2
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• pp.35-39
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• 2011

Error correcting codes with easy variability in code rate and codeword length in addition to powerful error correcting capability are required for present and future mobile multimedia communication systems. And low complexity is also needed for the compact mobile terminals. In general, the irregular random LDPC(low-density parity-check) code is known to have the superior performance among various LDPC codes. But it has inefficiency since the various parity check matrices for various services should be stored for encoding and decoding. The structured LDPC codes which can easily provide various rates and lengths are studied recently. Therefore, the flexibility, memory size, and error performance of various structured LDPC codes are compared and analyzed in this paper. And the most appropriate structured LDPC code is also suggested.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.5C
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• pp.432-438
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• 2010

In this paper we study the effect of bit-to-symbol mappings on the convergence behavior of turbo equalizers employing low-density parity-check (LDPC) codes over high order modulations. We analyze the effective SNR of the outputs from linear minimum mean-squared error (MMSE) equalizers and the convergence property of LDPC decoding for different symbol mappings. Numerical results show that the bit-reliability (BR) mapping provides better performance than random mapping in LDPC-coded turbo equalizers over high order modulations. We also verify the effect of symbol mappings through the noise threshold and error performance.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.10C
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• pp.758-763
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• 2008

We introduce a noise-predictive turbo equalization using noise filter in perpendicular magnetic recording(PMR) channel. The noise filter mitigates the colored noise in high-density PMR channel. In this paper, the channel detectors used are SOVA (Soft Output Viterbi Algorithm) and BCJR algorithm which proposed by Bahl et al., and the outer decoder used is LDPC (Low Density Parity Check) code that is implemented by sum-product algorithm. Two kinds of LDPC codes are experimented. One is the 0.5Kbyte (4336,4096) LDPC code with the code rate of 0.94, and the other is 1Kbyte (8432,8192) LDPC code with the code rate of 0.97.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.39C no.7
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• pp.515-520
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• 2014

In this paper, the protograph-based block low density parity check (LDPC) code, which improves the performance and reduces the encoder/decoder complexity than the conventional Digital Video Broadcasting Satellite Second Generation (DVB-S2) LDPC code used for the marine satellite communication, is proposed. The computer simulation results verify that the proposed protograph-based LDPC code has the better performance in both the bit error rate (BER) and the frame error rate (FER) than the conventional DVB-S2 LDPC code. Furthermore, by analyzing the encoding and decoding computational complexity, we show that the protograph-based block LDPC code has the efficient encoder/decoder structure.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.38A no.6
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• pp.471-478
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• 2013

Powerful error control and increase in the number of bits per symbol should be provided for future high-quality communication systems. Each message bit may have different importance in multimedia data. Hence, UEP(unequal error protection) may be more efficient than EEP(equal error protection) in such cases. And the LDPC(low-density parity-check) code shows near Shannon limit error correcting performance. Therefore, the effect of UEP with LDPC codes is analyzed for high-quality message data in this paper. The relationship among MSE(mean square error), BER(bit error rate) and the number of bits per symbol is analyzed theoretically. Then, total message bits in a symbol are classified into two groups according to importance to prove the relationship by simulation. And the UEP performance is obtained by simulation according to the number of message bits in each group with the constraint of a fixed total code rate and codeword length. As results, the effect of UEP with the LDPC codes is analyzed by MSE according to the number of bits per symbol, the ratio of the message bits, and protection level of the classified groups.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2010.10a
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• pp.722-725
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• 2010

In this paper, BER performance and error convergence speed of layered LDPC(Low Density Parity Check) decoder which supports IEEE 802.16e WiMAX standard is analyzed, and optimal design conditions for hardware implementation are derived. A LDPC decoder is modeled and simulated at AWGN channel with QPSK modulation by Matlab. The parity check matrix(PCM) for IEEE 802.16e standard which has block lengths of 576, 1440, 2304 and code rates of 1/2, 2/3A, 2/3B, 3/4A, 3/4B, 5/6 are used. Fixed-point simulation results show that fixed-point bit-width should be more than 8 bits for acceptable decoding performance.

• Journal of Communications and Networks
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• v.16 no.6
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• pp.639-644
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• 2014

In low-density parity-check (LDPC) coded multiple-input multiple-output (MIMO) communication systems, probabilistic information are exchanged between an LDPC decoder and a MIMO detector. TheMIMO detector has to calculate probabilistic values for each bit which can be very complex. In [1], the authors presented a class of linear block codes named low-density MIMO codes (LDMC) which can reduce the complexity of MIMO detector. However, this code only supports the outer-iterations between the MIMO detector and decoder, but does not support the inner-iterations inside the LDPC decoder. In this paper, a new approach to construct LDMC codes is introduced. The new LDMC codes can be encoded efficiently at the transmitter side and support both of the inner-iterations and outer-iterations at the receiver side. Furthermore they can achieve the design rates and perform very well over MIMO channels.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.9 s.351
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• pp.31-37
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• 2006

Low-density parity-check (LDPC) codes are recently emerged due to its excellent performance. The standard for European high definition satellite digital video broadcast, DVB-S2 has adopted LDPC codes as a channel coding scheme. This paper proposes a DVB-S2 LDPC decoder architecture using a hybrid parity check matrix which is efficient in hardware implementation for both decoders and encoders. The hybrid H-matrices are constructed so that both the semi-random technique and the partly parallel structure can be applied to design encoders and decoders. Using the hybrid H-matrix scheme, the architecture of LDPC decoder for DVB-S2 can be very practical and efficient. In addition, we show a new Variable Node processor Unit (VNU) architecture to reuse the VNU for various code rates and optimized block memory placement to reuse. We design a DVB-S2 LDPC decoder of code rate 1/2 usng the proposed architecture. We estimate the performance of the DVB-S2 LDPC decoder and compare it with other decoders.

• Transactions of the Society of Information Storage Systems
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• v.3 no.3
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• pp.126-128
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• 2007

일반적으로 주어진 하나의 H matrix 로 다수의 코드율을 가지는 코드화가 가능하다. 하지만 Low Density Parity Check(LDPC) 코드의 H matrix는 H matrix 내의 1의 개수와 위치에 따라 그 성능이 달라짐으로 해서 하나의 H matrix로 다수의 코드율을 대응하기 위한 설계 방법이 요구된다. H matrix 의 성능은 일반적으로 girth나 minimum distance에 의해 좌우되고 H matrix의 1의 위치에 따라 달라진다. 본 논문에서는 H matrix의 girth 와 minimum distance에 입각한 다수 개의 코드율이 대응 가능한 LDPC code의 H matrix 설계 방법을 제시하고자 한다. 이렇게 함으로써 하나의 H matrix로 다수의 코드율에 따른 각각의 성능을 일정 수준 이상 유지하는 multi-rate LDPC code가 가능하다.