• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.10a
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• pp.415-418
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• 2011

This paper describes a circuit-level optimization of DFU(decoding function unit) for LDPC decoder which is used in wireless communication systems such as WiMAX and WLAN. The conventional DFU which is based on min-sum decoding algorithm needs conversions between two's complement values and sign-magnitude values, resulting in complex hardware. In this paper, a new design of DFU that is based on sign-magnitude arithmetic is proposed to achieve a simplified circuit and high-speed operation.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.1051-1052
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• 2006

In this paper, we propose a puncturing scheme to design low-density parity-matrix (LDPC) codes for unequal error protection (UEP). Two different puncturing schemes are compared. Simulation results show that proposed puncturing scheme outperforms regular puncturing scheme for more important bits. Future work is to find an optimized puncturing patten for UEP irregular LDPC codes.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2010.10a
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• pp.722-725
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• 2010

In this paper, BER performance and error convergence speed of layered LDPC(Low Density Parity Check) decoder which supports IEEE 802.16e WiMAX standard is analyzed, and optimal design conditions for hardware implementation are derived. A LDPC decoder is modeled and simulated at AWGN channel with QPSK modulation by Matlab. The parity check matrix(PCM) for IEEE 802.16e standard which has block lengths of 576, 1440, 2304 and code rates of 1/2, 2/3A, 2/3B, 3/4A, 3/4B, 5/6 are used. Fixed-point simulation results show that fixed-point bit-width should be more than 8 bits for acceptable decoding performance.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2009.10a
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• pp.405-409
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• 2009

In this paper, the effects of LLR (Log-Likelihood Ratio) approximation on LDPC (Low-Density Parity-Check) decoder performance are analyzed, and optimal design conditions of LDPC decoder are derived. The min-sum LDPC decoding algorithm which is based on an approximation of LLR sum-product algorithm is modeled and simulated by MATLAB, and it is analyzed that the effects of LLR approximation bit-width and maximum iteration cycles on the bit error rate (BER) performance of LDCP decoder. The parity check matrix for IEEE 802.11n standard which has block length of 1,944 bits and code rate of 1/2 is used, and AWGN channel with QPSK modulation is assumed. The simulation results show that optimal BER performance is achieved for 7 iteration cycles and LLR bit-width of (7,5).

• Journal of Communications and Networks
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• v.16 no.6
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• pp.639-644
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• 2014

In low-density parity-check (LDPC) coded multiple-input multiple-output (MIMO) communication systems, probabilistic information are exchanged between an LDPC decoder and a MIMO detector. TheMIMO detector has to calculate probabilistic values for each bit which can be very complex. In [1], the authors presented a class of linear block codes named low-density MIMO codes (LDMC) which can reduce the complexity of MIMO detector. However, this code only supports the outer-iterations between the MIMO detector and decoder, but does not support the inner-iterations inside the LDPC decoder. In this paper, a new approach to construct LDMC codes is introduced. The new LDMC codes can be encoded efficiently at the transmitter side and support both of the inner-iterations and outer-iterations at the receiver side. Furthermore they can achieve the design rates and perform very well over MIMO channels.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.10
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• pp.2367-2372
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• 2015

One of various low-density parity-check(LDPC) codes that has been adopted in many communication standards due to its error correction ability is a quasi-cyclic LDPC(QC-LDPC) code, which leads to comparable decoder complexity. One of the main blocks in the QC-LCDC code decoder is a multi-size circular shifter(MSCS) that can perform various size rotation. The MSCS can be implemented with many structures, one of which is based on Banes network. The Benes network structure can perform the normal MSCS operation efficiently, but it cannot use the properties coming from specifications like rotation sizes. This paper proposesd a scheme where the Benes network structure can use the rotation size property with the modification of the control signal generation. The proposed scheme is applied to the MSCS of IEEE 802.16e WiMAX QC-LDPC decoder to reduce the number of MUXes and the critical path delay.

• ETRI Journal
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• v.39 no.3
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• pp.319-325
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• 2017

The decoding process of a quasi-cyclic low-density parity check code requires a unique type of rotator. These rotators, called multi-size cyclic-shifters (MSCSs), rotate input data with various sizes, where the size is the amount of data to be rotated. This paper proposes a low-complexity MSCS structure for the case when the sizes have a nontrivial common divisor. By combining the strong points of two previous structures, the proposed structure achieves the smallest area. The experimental results show that the area reduction was more than 14.7% when the proposed structure was applied to IEEE 802.16e as an example.

• Journal of Communications and Networks
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• v.16 no.5
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• pp.479-484
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• 2014

In this paper, we consider the construction of cyclic and quasi-cyclic structured q-ary low-density parity-check (LDPC) codes over a designated small field. The construction is performed with a pre-defined sliding-window, which actually executes the regular mapping from original field to the targeted field under certain parameters. Compared to the original codes, the new constructed codes can provide better flexibility in choice of code rate, code length and size of field. The constructed codes over small fields with code length from tenths to hundreds perform well with q-ary sum-product decoding algorithm (QSPA) over the additive white Gaussian noise channel and are comparable to the improved spherepacking bound. These codes may found applications in wireless sensor networks (WSN), where the delay and energy are extremely constrained.

• Journal of the Institute of Electronics and Information Engineers
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• v.54 no.6
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• pp.17-21
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• 2017

Since holographic data storage has the advantage of high recording density and data transfer rate, it is a candidate for the next generation storage systems. However, Holographic data storage system is affected by interpage interference and two dimensional intersymbol interference. Also, burst error occurs by physical impact. In this paper, we propose an LDPC product code using modified log-likelihood ratio and extrinsic information to correct burst error and improve performance of holographic data storage. The performance of proposed LDPC product code is 0.5dB better than that of the conventional LDPC code.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.10
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• pp.72-79
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• 2014

This paper presents a method for constructing a pipeline-aware quasi-cyclic irregular repeat accumulate low-density parity-check (PA-QC-IRA-LDPC) codes and efficient rate-1/2 (2016, 1008) PA-QC-IRA-LDPC decoder architecture. A novel pipeline scheduling method is proposed. The proposed methods efficiently reduce the critical path using pipeline without any bit error rate (BER) degradation. The proposed pipeline-aware LDPC decoder provides a significant improvement in terms of throughput, hardware efficiency, and energy efficiency. Synthesis and layout of the proposed architecture is performed using 90-nm CMOS standard cell technology. The proposed architecture shows more than 53% improvement of area efficiency and much better energy efficiency compared to the previously reported architectures.