• Title/Summary/Keyword: LDPC(Low Density Parity Code)

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A Study on Turbo Equalization for MIMO Systems Based on LDPC Codes (MIMO 시스템에서 LDPC 부호 기반의 터보등화 방식 연구)

  • Baek, Chang-Uk;Jung, Ji-Won
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.41 no.5
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    • pp.504-511
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    • 2016
  • In this paper, MIMO system based on turbo equalization techniques which LDPC codes were outer code and space time trellis codes (STTC) were employed as an inner code are studied. LDPC decoder and STTC decoder are connected through the interleaving and de-interleaving that updates each other's information repeatedly. In conventional turbo equalization of MIMO system, BCJR decoder which decodes STTC coded bits required two-bit wise decoding processing. Therefore duo-binary turbo codes are optimal for MIMO system combined with STTC codes. However a LDPC decoder requires bit unit processing, because LDPC codes can't be applied to these system. Therefore this paper proposed turbo equalization for MIMO system based on LDPC codes combined with STTC codes. By the simulation results, we confirmed performance of proposed turbo equalization model was improved about 0.6dB than that of conventional LDPC codes.

A Memory-efficient Partially Parallel LDPC Decoder for CMMB Standard (메모리 사용을 최적화한 부분 병렬화 구조의 CMMB 표준 지원 LDPC 복호기 설계)

  • Park, Joo-Yul;Lee, So-Jin;Chung, Ki-Seok;Cho, Seong-Min;Ha, Jin-Seok;Song, Yong-Ho
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.48 no.1
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    • pp.22-30
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    • 2011
  • In this paper, we propose a memory efficient multi-rate Low Density Parity Check (LDPC) decoder for China Mobile Multimedia Broadcasting (CMMB). We find the best trade-off between the performance and the circuit area by designing a partially parallel decoder which is capable of passing multiple messages in parallel. By designing an efficient address generation unit (AGU) with an index matrix, we could reduce both the amount of memory requirement and the complexity of computation. The proposed regular LDPC decoder was designed in Verilog HDL and was synthesized by Synopsys' Design Compiler using Chartered $0.18{\mu}m$ CMOS cell library. The synthesized design has the gate size of 455K (in NAND2). For the two code rates supported by CMMB, the rate-1/2 decoder has a throughput of 14.32 Mbps, and the rate-3/4 decoder has a throughput of 26.97 Mbps. Compared with a conventional LDPC for CMMB, our proposed design requires only 0.39% of the memory.

A Novel LDPC Decoder with Adaptive Modified Min-Sum Algorithm Based on SNR Estimation (SNR 예측 정보 기반 적응형 Modified UMP-BP LDPC 복호기 설계)

  • Park, Joo-Yul;Cho, Keol;Chung, Ki-Seok
    • IEMEK Journal of Embedded Systems and Applications
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    • v.4 no.4
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    • pp.195-200
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    • 2009
  • As 4G mobile communication systems require high transmission rates with reliability, the need for efficient error correcting code is increasing. In this paper, a novel LDPC (Low Density Parity Check) decoder is introduced. The LDPC code is one of the most popular error correcting codes. In order to improve performance of the LDPC decoder, we use SNR (Signal-to-Noise Ratio) estimation results to adjust coefficients of modified UMP-BP (Uniformly Most Probable Belief Propagation) algorithm which is one of widely-used LDPC decoding algorithms. An advantage of Modified UMP-BP is that it is amenable to implement in hardware. We generate the optimal values by simulation for various SNRs and coefficients, and the values are stored in a look-up table. The proposed decoder decides coefficients of the modified UMP-BP based on SNR information. The simulation results show that the BER (Bit Error Rate) performance of the proposed LDPC decoder is better than an LDPC decoder using a conventional modified UMP-BP.

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Performance of LDPC Coded OFDM/DS Under Fading and Jamming Environment (페이딩과 재밍 환경에서 LDPC 부호화된 OFDM/DS 시스템의 성능)

  • Seo, Dong-Cheul;Lee, Woo-Chan;Kim, Jong-Hun
    • Journal of the Korea Institute of Military Science and Technology
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    • v.11 no.5
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    • pp.23-33
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    • 2008
  • In this paper, we verify the performance of LDPC coded OFDM/DS system by Monte-Carlo simulation of BER on Eb/No. The simulation results show that LDPC coded OFDM/DS has a strong anti-jamming characteristic over pulse-noise jammer and partial-band noise jammer. The performance of LDPC coded OFDM/DS system is evaluated on both faded waveforms and non-faded waveforms. For non-faded waveforms, high coding gain is attained due to LDPC, even when waveforms have short PN sequence and JSR is only 5dB. Especially, the increase in the repeated number of LDPC decoding enhances coding gain. However, faded waveforms cannot achieve sufficient average effect when PN sequence is short. High coding gain of faded waveforms can be achieved by extending length of PN sequence. In addition, we compare LDPC coded OFDM/DS system with Convolutional coded OFDM/DS system. The simulation results illustrate that when LDPC coded OFDM/DS system with short PN sequence has sufficient average effects, the system shows lower BER than Convolutional coded OFDM/DS system with long PN sequence.

Improved Reliability-Based Iterative Decoding of LDPC Codes Based on Dynamic Threshold

  • Ma, Zhuo;Du, Shuanyi
    • ETRI Journal
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    • v.37 no.4
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    • pp.736-742
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    • 2015
  • A serial concatenated decoding algorithm with dynamic threshold is proposed for low-density parity-check codes with short and medium code lengths. The proposed approach uses a dynamic threshold to select a decoding result from belief propagation decoding and order statistic decoding, which improves the performance of the decoder at a negligible cost. Simulation results show that, under a high SNR region, the proposed concatenated decoder performs better than a serial concatenated decoder without threshold with an Eb/N0 gain of above 0.1 dB.

Parallel LDPC Decoding on a Heterogeneous Platform using OpenCL

  • Hong, Jung-Hyun;Park, Joo-Yul;Chung, Ki-Seok
    • KSII Transactions on Internet and Information Systems (TIIS)
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    • v.10 no.6
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    • pp.2648-2668
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    • 2016
  • Modern mobile devices are equipped with various accelerated processing units to handle computationally intensive applications; therefore, Open Computing Language (OpenCL) has been proposed to fully take advantage of the computational power in heterogeneous systems. This article introduces a parallel software decoder of Low Density Parity Check (LDPC) codes on an embedded heterogeneous platform using an OpenCL framework. The LDPC code is one of the most popular and strongest error correcting codes for mobile communication systems. Each step of LDPC decoding has different parallelization characteristics. In the proposed LDPC decoder, steps suitable for task-level parallelization are executed on the multi-core central processing unit (CPU), and steps suitable for data-level parallelization are processed by the graphics processing unit (GPU). To improve the performance of OpenCL kernels for LDPC decoding operations, explicit thread scheduling, vectorization, and effective data transfer techniques are applied. The proposed LDPC decoder achieves high performance and high power efficiency by using heterogeneous multi-core processors on a unified computing framework.

Performance and Iteration Number Statistics of Flexible Low Density Parity Check Codes (가변 LDPC 부호의 성능과 반복횟수 통계)

  • Seo, Young-Dong;Kong, Min-Han;Song, Moon-Kyou
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.12 no.1
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    • pp.189-195
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    • 2008
  • The OFDMA Physical layer in the WiMAX standard of IEEE 802.16e adopts 114 LDPC codes with various code rates and block sizes as a channel coding scheme to meet varying channel environments and different requirements for transmission performance. In this paper, the performances of the LDPC codes are evaluated according to various code rates and block-lengths throueh simulation studies using min-sum decoding algorithm in AWGN chamois. As the block-length increases and the code rate decreases, the BER performance improves. In the cases with code rates of 2/3 and 3/4, where two different codes ate specified for each code rate, the codes with code rates of 2/3A and 3/4B outperform those of 2/3B and 3/4A, respectively. Through the statistical analyses of the number of decoding iterations the decoding complexity and the word error rates of LDPC codes are estimated. The results can be used to trade-off between the performance and the complexity in designs of LDPC decoders.

Systematic Performance Analysis of the PEG and IPEG in the LDPC Codes (LDPC Codes에서 PEG 알고리듬과 IPEG 알고리듬의 성능 비교 평가 및 분석)

  • Kim, Hyun-Seung;Ko, Jae-Hyun;Jang, Min;Kim, Sang-Hyo
    • Proceedings of the Korean Society of Broadcast Engineers Conference
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    • 2009.11a
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    • pp.25-27
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    • 2009
  • 1962년 R.G Gallager가 제안한 LDPC(Low Density Parity Check)부호는 Shannon의 채널 용량의 한계에 근접한 우수한 오류정정 부호이다. 우수한 LDPC부호 생성 조건 중 가장 중요한 부분은 바로 최소 사이클 길이(girth)를 최대화 하는 과정인데, PEG(Progressive Edge Growth)알고리듬은 이 조건을 만족시키는 우수한 알고리듬으로 인정받고 있다. 이후 높은 SNR범위에서 PEG알고리듬의 성능을 개선한 IPEG (Improved PEG) 알고리듬을 포함한 다양한 알고리듬이 제안 되었다.본 논문은 PEG와 IPEG 알고리듬을 이용해 생성한 LDPC 부호를 이용하여 부호길이, 부호율을 변화시키면서 실험하여 그 결과를 비교 분석하였고, 더 좋은 성능을 가질 수 있는 알고리듬에 대해 논의한다.

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Rate-Adaptive LDPC Code Design for Distributed Video Coding System (분산 동영상 부호화 시스템을 위한 부호율 적응적인 LDPC 부호 설계)

  • Noh, Hyeun-Woo;Lee, Chang-Woo
    • Proceedings of the Korean Society of Broadcast Engineers Conference
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    • 2011.07a
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    • pp.284-286
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    • 2011
  • LDPC(low density parity check) 부호는 낮은 복잡성과 Shannon의 한계에 근접하는 오류 정정 능력을 보이기 때문에 turbo 부호와 함께 많은 응용분야에 적용되고 있다. 본 논문에서는 분산 동영상 부호화(distributed video coding: DVC) 시스템을 위한 부호율 적응적인(rate adaptive) LDPC 부호를 설계하기 위하여 패리티 점검 노드를 병합하는 방법을 제안한다. ACE(approximation cycles EMD) 알고리즘을 기반으로 효율적인 LDPC 부호를 설계하고 부호율 적응적인 특성을 갖기 위해 일정한 범위를 지정하고 지정된 범위에 따라 패리티 점검 노드를 병합한다. 그리고 ACE 알고리즘의 계수와 degree distribution을 변화시키면서 성능을 해석한다.

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Optimal Bit Split Methods and Performance Analysis for Applying to Multilevel Modulation of Iterative Codes (반복 부호의 다치 변조방식 적용을 위한 최적의 비트 분리 방법 및 성능평가)

  • Bae, Jong-Tae;Jung, Ji-Won;Choi, Seok-Soon;Kim, Min-Hyuk;Chang, Dae-Ig
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.32 no.3C
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    • pp.216-225
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    • 2007
  • This paper presents bit splitting methods to apply multilevel modulation to iterative codes such as turbo code, low density parity check code and turbo product code. Log-likelihood ratio method splits multilevel symbols to bits using the received in-phase and quadrature component based on Gaussian approximation. However it is too complicate to calculate and implement hardware due to exponential and log calculation. therefore this paper presents Euclidean, MAX and Sector method to reduce the high complexity of LLR method. We propose optimal bit splitting method for three iterative codes.