• Nuclear Engineering and Technology
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• v.29 no.5
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• pp.399-405
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• 1997

In this study a new phase separated spectral analysis algorithm is proposed to identify CSB vibration mode directly from ex-core neutron signals. Ex-core neutron signals can be decomposed into the global, core support barrel (CSB) beam mode, and CSB shell mode components by the new phase separation algorithm based on the characteristics of Fourier transform. By using the proposed algorithm and the conventional spectral analysis the vibration mode of the CSB and the fuel assembly of Ulchin-1 NPP were identified from measured ex-core neutron signals.

• IEIE Transactions on Smart Processing and Computing
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• v.5 no.1
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• pp.43-48
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• 2016

We propose plain fingerprint classification based on a core stochastic algorithm that effectively uses a core stochastic model, acquiring more fingerprint minutiae and direction, in order to increase matching performance. The proposed core stochastic algorithm uses core presence/absence and contains a ridge direction and distribution map. Simulations show that the fingerprint classification accuracy is improved by more than 14%, on average, compared to other algorithms.

• Proceedings of the KIEE Conference
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• 2008.07a
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• pp.65-66
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• 2008

This paper proposes a compensating algorithm for the secondary current of the measurement current transformer (CT) that removes the effects of the hysteresis characteristics of the iron-core. The exciting current resulting from the hysteresis characteristics of the core causes an error between the primary current and the secondary current of the CT. The proposed algorithm decomposes the exciting current into the magnetizing current and the core loss current and each of them is estimated. The core loss current is calculated from the secondary voltage and the secondary voltage-core loss current curve. The core flux linkage is calculated and then inserted into the flux-current curve to estimate the magnetizing current. The exciting current at every sampling interval is obtained by summing the core-loss and magnetizing currents and then added to the measured current to compensate the secondary current. The performance of the proposed algorithm is validated under various conditions using EMTP generated data. The test results of the real CT were also included. The results indicate that the proposed algorithm can improve the accuracy of the measurement CT significantly, and thus reduce the size and the cost of the CT.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.10
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• pp.46-52
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• 2009

A Multi-Core/Multi-Thread architecture is adopted for the Shader processor to enhance the processing performance. The Shader processor is designed to utilize its processing core IP for multiple purposes, such as Vertex-Shading, Rasterization, Pixel-Shading, etc. In this paper, we propose a 'Rasterization based on Vector Algorithm' that makes parallel pixels processing possible with Multi-Core and Multi-Thread architecture on the Shader Core. The proposed algorithm takes only 2% operation counts of the Scan-Line Algorithm and processes pixels independently.

• IEMEK Journal of Embedded Systems and Applications
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• v.8 no.2
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• pp.87-93
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• 2013

In this paper, we implemented and evaluated the performance of a vector-based rasterization algorithm of 3D graphics using a SIMD-based many-core processor that consists of 4,096 processing elements. In addition, we compared the performance and efficiency of the rasterization algorithm using the many-core processor and commercial GPU (Graphics Processing Unit) system which consists of 7 GPUs and each of which have 512 cores. Experimental results showed that the SIMD-based many-core processor outperforms the commercial GPU system in terms of execution time (3.13x speedup), energy efficiency (17.5x better), and area efficiency (13.3x better). These results demonstrate that the SIMD-based many-core processor has potential as an embedded mobile processor.

• Journal of information and communication convergence engineering
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• v.10 no.1
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• pp.78-84
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• 2012

This paper presents a branch prediction algorithm and a 4-way set-associative cache for performance improvement of an embedded RISC core and a clock-gating algorithm with observability don’t care (ODC) operation to reduce the power consumption of the core. The branch prediction algorithm has a structure using a branch target buffer (BTB) and 4-way set associative cache that has a lower miss rate than a direct-mapped cache. Pseudo-least recently used (LRU) policy is used for reducing the number of LRU bits. The clock-gating algorithm reduces dynamic power consumption. As a result of estimation of the performance and the dynamic power, the performance of the OpenRISC core applied to the proposed architecture is improved about 29% and the dynamic power of the core with the Chartered 0.18 ${\mu}m$ technology library is reduced by 16%.

• 한국정보디스플레이학회:학술대회논문집
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• 2004.08a
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• pp.239-242
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• 2004

This paper presents a novel contrast enhance algorithm for images displayed with bright environment light. This algorithm is designed to preserve local contrast based on the luminance ratio of the pixel to its local surround in attention. This algorithm improves image quality of projectors in a bright room.

• Proceedings of the KIEE Conference
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• 2003.07a
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• pp.320-322
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• 2003

This paper describes a current differential relaying algorithm for a three-phase transformer considering the nonlinear magnetization characteristics of the core. The iron-loss current is obtained from the calculated induced voltage and the core-loss resistance. The magnetizing current is calculated from the estimated core flux and the magnetization curve. The proposed algorithm uses the modified differential current, which is obtained by subtracting the iron-loss current and the magnetizing current from the conventional differential current. The various test results show that the algorithm can discriminate internal fault from magnetic inrush, overexcitation and an external fault.

• Journal of Information Technology and Architecture
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• v.11 no.2
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• pp.225-233
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• 2014

In this paper an architecture for 3D audio core algorithm evaluation database system. Due to increase of 3D audio system through multimedia device, an evaluation system is required for evaluating the 3D core algorithms for developing 3D audio system. Conventional evaluation systems have some problems. Researchers have to learn usage of evaluation system, in addition it is inefficient to use and search audio sources because audio sources are not indexed in general. To solve these problems, we design the architecture of 3D audio core algorithm evaluation database system enabling to automatically evaluate core algorithms using database management system. Also we define XML metadata scheme for information of saved audio source in database. This approach allows improving efficiency of search audio source and use of audio database.

• Journal of the Korea Society of Computer and Information
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• v.18 no.9
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• pp.1-10
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• 2013

In this paper, we implement the SIFT(Scale-Invariant Feature Transform) algorithm for feature point extraction using a many-core processor, and analyze the performance, area efficiency, and system area efficiency of the many-core processor. In addition, we demonstrate the potential of the proposed many-core processor by comparing the performance of the many-core processor with that of high-performance CPU and GPU(Graphics Processing Unit). Experimental results indicate that the accuracy result of the SIFT algorithm using the many-core processor was same as that of OpenCV. In addition, the many-core processor outperforms CPU and GPU in terms of execution time. Moreover, this paper proposed an optimal model of the SIFT algorithm on the many-core processor by analyzing energy efficiency and area efficiency for different octave sizes.