Browse > Article
http://dx.doi.org/10.14372/IEMEK.2013.8.2.087

Implementation and Performance Evaluation of Vector based Rasterization Algorithm using a Many-Core Processor  

Shon, Dong-Koo (Ulsan University)
Kim, Jong-Myon (Ulsan University)
Publication Information
Abstract
In this paper, we implemented and evaluated the performance of a vector-based rasterization algorithm of 3D graphics using a SIMD-based many-core processor that consists of 4,096 processing elements. In addition, we compared the performance and efficiency of the rasterization algorithm using the many-core processor and commercial GPU (Graphics Processing Unit) system which consists of 7 GPUs and each of which have 512 cores. Experimental results showed that the SIMD-based many-core processor outperforms the commercial GPU system in terms of execution time (3.13x speedup), energy efficiency (17.5x better), and area efficiency (13.3x better). These results demonstrate that the SIMD-based many-core processor has potential as an embedded mobile processor.
Keywords
Rasterization algorithm; 3D graphics; Many-core processors; Graphics processing unit(GPU);
Citations & Related Records
Times Cited By KSCI : 1  (Citation Analysis)
연도 인용수 순위
1 D.K. Shon, J.M. Kim, "Rasterization Algorithm based on Vector for Many Core Processor", Proceedings on Summer Conference of KISPS, pp.66-68, 2012 (in Korean).
2 B.K. Choi, C.H. Kim, J.M. Kim, "Implementation of SIMD-based Many-Core Processor for Efficient Image Data Processing", Journal of the KSCI, Vol. 16, No. 1, pp.1-9, 2011 (in Korean).
3 Y.M. Kim, J.M. Kim, "Design and Verification of High-Performance Parallel Processor Hardware for JPEG Encoder", Journal of IEMEK, Vol. 6, No. 2, pp.100-107, 2011 (in Korean).
4 S.M. Chai, T.M. Taha, D.S. Wills, J.D. Meindl, "Heterogeneous architecture models for interconnect-motivated system design," IEEE Trans. VLSI Systems, special issue on system level interconnect prediction, Vol. 8, No. 6, pp.660-670, 2000.
5 J.C. Eble, V.K. De, D.S. Wills, J.D. Meindl, "A generic system simulator (GENESYS) for ASIC technology and architecture beyond 2001," Proceedings on International Conference of the Ninth Ann. IEEE ASIC, pp.193-196, 1996.
6 H.J. Woo, "A design of the embedded 3D graphics rendering processor for portable devices", Thesis for master course, Yonsei University, 2004 (in Korean).
7 N. Singhal, J.W. Yoo, H.Y. Choi, I.K. Park, "Implementation and Optimization of Image Processing Algorithms on Embedded GPU," IEICE Trans. Inf. & Syst., Vol. E95-D, No. 5, pp.1475-1484, 2012.   DOI
8 I.K. Park, N. Singhal, M.H. Lee, S. Cho, C.W. Kim, "Design and Performance Evaluation of Image Processing Algorithm on GPUs," IEEE Trans. Parallel Distrib. Syst., Vol. 22, No. 1, pp.91-104, 2011.   DOI   ScienceOn
9 Y.H. Ahn, Y.S. Hwang, K.S. Chung, "Kernel Level Power Management Solution for Multi-Core", Journal of IEMEK, Vol. 4, No. 2, pp.50-54, 2009 (in Korean).