• Journal of Industrial Technology
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• v.29 no.B
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• pp.187-191
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• 2009

Recently, we have used LEDs to illumination because it has a high luminous efficiency and prolong lifespan. However the light power and lifetime is reduced by junction temperature increment of LED. So it is important to measure the junction temperature accurately. In case of using a electrical method measuring junction temperature of LED. Temperature measurement errors are spontaneously generated because of a parasitic capacitances in LED. In this paper, we proposed a method that reducing LED's parasitic capacitance effects for electrical measurement. It was demonstrated by the experimental result that is more correct than established method.

• Journal of the Korean Magnetics Society
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• v.12 no.2
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• pp.68-72
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• 2002

In this research, the effects of capacitance to the access time were studied at the junction area of tunneling magnetoresistance when these were used as memory devices. These results were obtained by applying electric signal input and magnetic field was not used. We applied bipolar square waves of 1MHz to the MTJ samples to obtain the results and time constant ($\tau$) calculated by observing wave responses utilizing an oscilloscope. And time constant was compared with junction area. Each part of MTJ sample, such as electrical pad, lead and contact area, was modeled as an electrical equivalent circuit based on experimental results. For the 200㎛$\times$200㎛ cell, junction capacitance was 90 pF. Also, measurement and simulation results were compared, which showed those similarity.

• Journal of Sensor Science and Technology
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• v.23 no.3
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• pp.185-191
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• 2014

The width of depletion region in a varactor diode can be modulated by varying a reverse bias voltage. Thus, the preferred characteristics of depletion capacitance can obtained by the change in the width of depletion region so that it can select only the desirable frequencies. In this paper, the TV tuner varactor diode fabricated by hyper-abrupt profile control technique is presented. This diode can be operated within 3.3 V of driving voltage with capability of UHF band tuning. To form the hyperabrupt profile, firstly, p+ high concentration shallow junction with $0.2{\mu}m$ of junction depth and $1E+20ions/cm^3$ of surface concentration was formed using $BF_2$ implantation source. Simulation results optimized important factors such as epitaxial thickness and dose quality, diffusion time of n+ layer. To form steep hyper-abrupt profile, Formed n+ profile implanted the $PH_3$ source at Si(100) n-type epitaxial layer that has resistivity of $1.4{\Omega}cm$ and thickness of $2.4{\mu}m$ using p+ high concentration Shallow junction. Aluminum containing to 1% of Si was used as a electrode metal. Area of electrode was $30,200{\mu}m^2$. The C-V and Q-V electric characteristics were investigated by using impedance Analyzer (HP4291B). By controlling of concentration profile by n+ dosage at p+ high concentration shallow junction, the device with maximum $L_F$ at -1.5 V and 21.5~3.47 pF at 0.3~3.3 V was fabricated. We got the appropriate device in driving voltage 3.3 V having hyper-abrupt junction that profile order (m factor) is about -3/2. The deviation of capacitance by hyper-abrupt junction with C0.3 V of initial capacitance is due to the deviation of thermal process, ion implantation and diffusion. The deviation of initial capacitance at 0.3 V can be reduced by control of thermal process tolerance using RTP on wafer.

• Proceedings of the Korean Magnestics Society Conference
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• 2001.04a
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• pp.34-35
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• 2001

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.8
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• pp.46-52
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• 1994

DC and AC current crowding effects for microwave and high speed bipolar transistors are investigated in detail using a new and accurate measurement technique based on Z-parameter equationa. Using the new measurement technique dc and ac current crowding effects have been explained clearly in bipolar junction transistors. To model ac crowding effects a capacitive element defined as base capacitance (C$_b$), called ac crowding capacitance is added to base resistance in parallel thereby treating the base resistance(R$_b$) as base impedance Z$_b$. It is shown that base resistance decreases with increasing collector current due to dc current crowding and approaches to a certain limited value at high collector current due to current crowding and approaches to a certain limited value at high collector currents regardless of the emitter size. It is also observed that due to ac current crowding base capacitance increases with increasing collector current. To quantigy the ac crowding effects for SPICE circuit simulation the base capacitance(C$_b$) including the base depletion and diffusion components has been modeled with an analytical expression form.

• Korean Journal of Materials Research
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• v.29 no.7
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• pp.408-411
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• 2019

ZTO/n-Si thin film is produced to investigate tunneling phenomena by interface characteristics by the depletion layer. For diversity of the depletion layer, the thin film of ZTO is heat treated after deposition, and the gpolarization is found to change depending on the heat treatment temperature and capacitance. The higher the heat treatment temperature is, the higher the capacitance is, because more charges are formed, the highest at $150^{\circ}C$. The capacitance decreases at $200^{\circ}C$ ZTO heat treated at $150^{\circ}C$ shows tunneling phenomena, with low non-resistance and reduced charge concentration. When the carrier concentration is low and the resistance is low, the depletion layer has an increased potential barrier, which results in a tunneling phenomenon, which results in an increase in current. However, the ZTO thin film with high charge or high resistance shows a Schottky junction feature. The reason for the great capacitance increase is the increased current due to tunneling in the depletion layer.

• Transactions on Electrical and Electronic Materials
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• v.14 no.4
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• pp.177-181
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• 2013

In this paper, silicon solar cells are analyzed regarding power conversion efficiency by changed capacitance in the depletion region. For the capacitance control in the depletion region of silicon solar cell was applied for 10, 20, 40, 80, 160 and 320 Hz frequency band character and alternating current(AC) voltage with square wave of 0.2~1.4 V. Academically, symmetry formation of positive and negative change of the p-n junction is similar to the physical effect of capacitance. According to the experiment result, because input of square wave with alternating current(AC) voltage could be observed to changed capacitance effect by indirectly method through non-linear power conversion (Voltage-Current) output. In addition, when input alternating current(AC) voltage in the silicon solar cell, changed capacitance of depletion region with the forward bias condition and reverse bias condition gave a direct effect to the charge mobility.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2000.07a
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• pp.63-66
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• 2000

In this paper, we present the simulation of the heterojunction bipolar transistor with different Emitter-Base junction structures. Our simulation results include effect of setback and graded layer. We prove the emitter efficiency's improvement through setback and graded layer. In 1995, the analytical equations of electric field, electrostatic potential, and junction capacitance for abrupt and linearly graded heterojunctions with or without a setback layer was derived. But setback layer and linearly graded layer's recombination current was considered numerically. Later, recombination current model included setback layer and graded layer will be proposed. New recombination current model also wile include abrupt heterojunction's recombination current model. In this paper, the material parameters of the heterojunction bipolar transistor with different Emitter-Base junction structures is introduced.

• JSTS:Journal of Semiconductor Technology and Science
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• v.7 no.4
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• pp.274-280
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• 2007

This paper demonstrates an efficiency improvement of the class E power amplifier (PA) by tuning-out the input capacitance ($C_{IN}$) of the power HBT with a shunt inductance. In order to obtain high output power, the PA needs the large emitter size of a transistor. The larger the emitter size, the higher the parasitic capacitance. The parasitic $C_{IN}$ affects the distortion of the voltage signal at the base node and changes the duty cycle to decrease the PA's efficiency. Adopting the L-C resonance, we obtain a remarkable efficiency improvement of as much as 7%. This PA exhibits output power of 29 dBm and collector efficiency of 71% at 1.9 GHz.

• Korean Journal of Metals and Materials
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• v.47 no.5
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• pp.311-315
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• 2009

2-dimensional (2D) dopant profiling in semiconductor device was carried out by electron holography and scanning capacitance microscopy methods with the same multi-layered p-n junction sample. The dopant profiles obtained from two methods are in good agreement with each other. It demonstrates that reliability of dopant profile measurement can be increased through precise comparison of 2D profiles obtained from various techniques.