• Proceedings of the KIEE Conference
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• 대한전기학회 1999년도 하계학술대회 논문집 D
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• pp.1956-1958
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• 1999

The analysis of hole injection efficiency at the p+/n-drift layer junction in non-punchthrough IGBT structure is presented. This analysis takes into account carrier concentration variations by conductivity modulation. Good agreement between this analysis and simulation is found over a wide range of carrier lifetime and current density. The proposed analytical model of the hole injection efficiency as a function of collector width, collector concentration has been verified by device simulator, ATLAS.

• Proceedings of the KIEE Conference
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• 대한전기학회 1995년도 하계학술대회 논문집 C
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• pp.1072-1074
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• 1995

Zinc-Borosilicate is used as a side insulastor wall to make high breakdown voltage with one Field Limiting Ring in a p-n junction. It is known that surface charge can be yield at the interface of Zinc-Borosilicate Glass/Silicon system. When the glass is used as a side insulator wall, surface charge varied potential distribution and breakdown voltage improved more than 660V without using more FLR.

• Proceedings of the Korean Magnestics Society Conference
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• 한국자기학회 2011년도 임시총회 및 하계학술연구발표회
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• pp.91-92
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• 2011

• Proceedings of the IEEK Conference
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• 대한전자공학회 2002년도 하계종합학술대회 논문집(2)
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• pp.365-368
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• 2002

WSW(Wrap Side Wall) is proposed to decrease junction electric field in this paper. WSW process is fabricated after first gate etch, followed NMI ion implantation and deposition & etch nitride layer New WSW structure has buffer layer to decrease electric field. Also we compared the hot carrier characteristics of WSW and conventional. Also, we design a test pattern including pulse generator, level shifter and frequency divider, so that we can evaluate AC hot carrier degradation on-chip.

• Proceedings of the Optical Society of Korea Conference
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• 한국광학회 1991년도 제6회 파동 및 레이저 학술발표회 Prodeedings of 6th Conference on Waves and Lasers
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• pp.135-138
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• 1991

A planar type PIN photodiode has been fabricated and discussed. We used OMVPE systems to grow the structure of u-InP/u-InP/n-InP. P-n junction was formed by Zn-diffusion method at 50$0^{\circ}C$, for 5 minitues. The device characteristics at 5V were as follows: Dark currents were distributed around 1nA. Capacitance was 1.6pF and responsivity was above 0.85 mA/mW for 1.3${\mu}{\textrm}{m}$ wavelength. Measured cut-off frequency(-3dB) at -5V was 1.1㎓.

• The Transactions of the Korean Institute of Electrical Engineers
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• 제33권6호
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• pp.203-211
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• 1984

MOS silicon solar cells have been developed using the fixed (interface) charge inherent to thermally oxidized silicon to induce an n-type inversion layer in 1-10 ohm-cm p-type silicon. Higher collection efficiencies are predicted than for diffused junction cells. Without special precautions a conversion efficiency of 14.2% is obtained. A MOS silicon solar cell is described in which an inversion layer forms the active area which is then contacted by means of a MOS grid. The highest efficiency is obtained when the resistivity of the substrate is high.

• Proceedings of the KIEE Conference
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• 대한전기학회 1995년도 하계학술대회 논문집 C
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• pp.1146-1148
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• 1995

To improve the breakdown characteristics of vertical power devices, field limiting ring(FLR) is popularly used. In this paper, at vertical power device having $300{\sim}600V$ breakdown voltage, FLR thecnique is considered, by two dimensional computer simulator, with the various of parameters; number of FLR, seperation distance of first FLR from the main juncton and second FLR from the first FLR, doping concentration and thickness of epi-layer, etc.. Below $40{\mu}m$ epi thickness, and for the case of one FLR, the maximum breakdown voltage, 580V is obtained.

• Proceedings of the IEEK Conference
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• 대한전자공학회 2005년도 추계종합학술대회
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• pp.731-734
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• 2005

In this study, the design of advanced LVDS(Low Voltage Differential Signaling) I/O interface circuit with new structural low triggering ESD (Electro-Static Discharge) protection circuit was investigated. Due to the differential transmission technique and low power consumption at the same time. Maximum transmission data ratio of designed LVDS transmitter was simulated to 5Gbps. And Zener Triggered SCR devices to protect the ESD phenomenon were designed. This structure reduces the trigger voltage by making the zener junction between the lateral PNP and base of lateral NPN in SCR structure. The triggering voltage was simulated to 5.8V. Finally, we performed the layout high speed I/O interface circuit with the low triggered ESD protection device in one-chip.

• Proceedings of the Korean Vacuum Society Conference
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• 한국진공학회 2015년도 제49회 하계 정기학술대회 초록집
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• pp.243.2-243.2
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• 2015

We report a high-performing nanoscale NiO thin film grown by thermal oxidation of sputtered Ni film. The structural, physical, optical and electrical properties of nanoscale NiO were comprehensively investigated. A quality transparent heterojunction (NiO/ZnO) was formed by large-area applicable sputtering deposition method that has an extremely low saturation current of 0.1 nA. Considerable large rectification ratio of more than 1000 was obtained for transparent heterojunction device. Mott-Schottky analyses were applied to develop the interface of NiO and ZnO by establishing energy diagrams. Nanoscale NiO has the accepter carrier concentration of the order of 1018 cm-3. Nanoscale NiO Schottky junction device properties were comprehensively studied using room temperature impedance spectroscopy.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• 제19권10호
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• pp.894-900
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• 2006

This paper reports the fabrication and characterization of $32{\times}32$ thermal cantilever array for nano-scaled memory device applications. The $32{\times}32$ thermal cantilever array with integrated tip heater has been fabricated with micro-electro-mechanical systems(MEMS) technology on silicon on insulator(SOI) wafer using 9 photo masking steps. All of single-level cantilevers(1,024 bits) have a p-n junction diode in order to eliminate any electrical cross-talk between adjacent cantilevers. Nonlinear electrical characteristic of fabricated thermal cantilever shows its own thermal heating mechanism. In addition, n-channel high-voltage MOSFET device is integrated on a wafer for embedding driver circuitry.