• Journal of Power Electronics
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• v.17 no.5
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• pp.1298-1307
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• 2017

The constant on-time current-mode controlled (COT-CMC) switching dc-dc converter is stable, with no subharmonic oscillation in its current loop when a voltage ripple in its outer voltage loop is ignored. However, when its output capacitance is small or its feedback gain is high, subharmonic oscillation may occur in a COT-CMC buck converter with a proportional-integral (PI) compensator. To investigate the subharmonic instability of COT-CMC buck converters with a PI compensator, an accurate reduced-order asynchronous-switching map model of a COT-CMC buck converter with a PI compensator is established. Based on this, the instability behaviors caused by output capacitance and feedback gain are investigated. Furthermore, an approximate instability condition is obtained and design-oriented stability boundaries in different circuit parameter spaces are yielded. The analysis results show that the instability of COT-CMC buck converters with a PI compensator is mainly affected by the output capacitance, output capacitor equivalent series resistance (ESR), feedback gain, current-sensing gain and constant on-time. The study results of this paper are helpful for the circuit parameter design of COT-CMC switching dc-dc converters. Experimental results are provided to verify the analysis results.

• Journal of Power Electronics
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• v.18 no.3
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• pp.714-722
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• 2018

This paper presents a wide-range speed control scheme of brushless DC (BLDC) motors based on a hall sensor with separated low- and normal-speed controllers. However, the use of the hall sensor signal is insufficient to detect motor speed in the low-speed region because of low sensor resolution and time delay. In the proposed method, a micro-stepping current control method according to the torque angle variation is presented. In this mode, the motor current frequency and rotating angle are determined by the reference speed without the actual speed fed by the hall sensor. The detected torque angle is used to adjust the current value in a limited band to control the current value in accordance with the load. The torque angle is detected exactly at the changing point of the hall sensor signal. The rotor can follow the rotating flux with the variable torque angle. In a normal speed range, the conventional vector control scheme is used to control the motor current with a PI speed controller using the hall sensor. The torque characteristics are analyzed on the basis of the back EMF and current shape. To adopt the vector control scheme, the continuous rotor position is estimated by the measured speed and hall sensor position. At the mode changing point between low and normal speed range, the proper initial current command and reference rotor position are calculated. The calculated current command can reduce the torque ripple during transient mode. The proposed method is simple but effective in extending the speed control range of a conventional BLDC motor with hall sensor without the need for a high-resolution encoder. The effectiveness of the proposed method is verified by various experiments on a practical BLDC motor.

• Journal of Power Electronics
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• v.18 no.3
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• pp.841-852
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• 2018

This paper presents a dual-algorithm search method (GWO-GSO) combining grey wolf optimization (GWO) and golden-section optimization (GSO) to realize maximum power point tracking (MPPT) for photovoltaic (PV) systems. First, a modified grey wolf optimization (MGWO) is activated for the global search. In conventional GWO, wolf leaders possess the same impact on decision-making. In this paper, the decision weights of wolf leaders are automatically adjusted with hunting progression, which is conducive to accelerating hunting. At the later stage, the algorithm is switched to GSO for the local search, which play a critical role in avoiding unnecessary search and reducing the tracking time. Additionally, a novel restart judgment based on the quasi-slope of the power-voltage curve is introduced to enhance the reliability of MPPT systems. Simulation and experiment results demonstrate that the proposed algorithm can track the global maximum power point (MPP) swiftly and reliably with higher accuracy under various conditions.

• Journal of Power Electronics
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• v.18 no.3
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• pp.931-943
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• 2018

Wireless power transfer (WPT) technology has been the focus of a lot of research due to its safety and convenience. The Z-source inverter (ZSI) was introduced into WPT systems to realize improved system performance. The ZSI regulates the dc-rail voltage in WPT systems without front-end converters and makes the inverter bridge immune to shoot-through states. However, when the WPT system is combined with a ZSI, the system parameters must be configured to prevent the ZSI from entering an "accidental shoot-through" (AST) state. This state can increase the THD and decrease system power and efficiency. This paper presents a mathematical analysis for the characteristics of a WPT system and a ZSI while addressing the causes of the AST state. To deal with this issue, the impact of the system parameters on the output are analyzed under two control algorithms and the primary compensation capacitance range is derived in detail. To validate the analysis, both simulations and experiments are carried out and the obtained results are presented.

• Journal of Power Electronics
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• v.18 no.3
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• pp.702-713
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• 2018

Power loss reduction and total harmonic distortion(THD) minimization are two important goals of improving three-level inverters. In this paper, an optimized pulse width modulation (PWM) strategy that can reduce switching losses and balance the neutral point with an optional THD of three-level neutral-point-clamped inverters is proposed. An analysis of the two-level discontinuous PWM (DPWM) strategy indicates that the optimal goal of the proposed PWM strategy is to reduce switching losses to a minimum without increasing the THD compared to that of traditional SVPWMs. Thus, the analysis of the two-level DPWM strategy is introduced. Through the rational allocation of the zero vector, only two-phase switching devices are active in each sector, and their switching losses can be reduced by one-third compared with those of traditional PWM strategies. A detailed analysis of the impact of small vectors, which correspond to different zero vectors, on the neutral-point potential is conducted, and a hysteresis control method is proposed to balance the neutral point. This method is simple, does not judge the direction of midpoint currents, and can adjust the switching times of devices and the fluctuation of the neutral-point potential by changing the hysteresis loop width. Simulation and experimental results prove the effectiveness and feasibility of the proposed strategy.

• Journal of Power Electronics
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• v.16 no.6
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• pp.2024-2034
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• 2016

This paper presents a DC-DC buck converter with a Phase-Locked Loop (PLL) that can compensates for power efficiency degradation over a wide input range. Its switching frequency is kept at 2 MHz and the delay difference between the High side driver and the Low side driver can be minimized with respect to Process, Voltage and Temperature (PVT) variations by adopting the PLL. The operation mode of the proposed DC-DC buck converter is automatically changed to Pulse Width Modulation (PWM) or PWM frequency modes according to the load condition (heavy load or light load) while supporting a maximum load current of up to 1.2 A. The PWM frequency mode is used to extend the CCM region under the light load condition for the PWM operation. As a result, high efficiency can be achieved under the light load condition by the PWM frequency mode and the delay compensation with the PLL. The proposed DC-DC buck converter is fabricated with a $0.18{\mu}m$ BCD process, and the die area is $3.96mm^2$. It is implemented to have over a 90 % efficiency at an output voltage of 5 V when the input range is between 8 V and 20 V. As a result, the variation in the power efficiency is less than 1 % and the maximum efficiency of the proposed DC-DC buck converter with the PLL is 95.4 %.

• Journal of Power Electronics
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• v.16 no.6
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• pp.2119-2128
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• 2016

Due to detection and control errors, some high-frequency harmonics with voltage-source characteristics cause circulating currents in modular inverters. Moreover, the circulating currents are usually affected by the output filters (OF) of each module due to their filter and resonance properties. The interaction among the circulating currents in the modules increase the power loss and reduce system stability and control precision. Therefore, this paper reports the results of a study on the SPWM high-frequency harmonics circulating currents for a double-module VSI. In the paper, an analysis of the circulating-current circuits is briefly described. Next, a mathematic model of the single-module output voltage based on the carrier frequency of SPWM is built. On this basis, through mathematic modeling of high-frequency harmonic circulating currents, the formation mechanism and distribution characteristics of circular currents and their influences are studied in detail. Finally, the influences of the OF on the circulating currents are studied by mainly taking an LC-type filter as an example. A theoretical analysis and experimental results demonstrate some important characteristics. First, the carrier phase shifting of the SPWM for each module is the major cause of the SPWM harmonic circulating currents, and the circulating currents are in an odd distribution around n-times the carrier frequency $n{\omega}_s$, where n = 1, 2, 3, ${\ldots}$. Second, the harmonic circular currents do not flow into the parallel system. Third, the OF can effectively suppress the non-circulating part of the high-frequency harmonic currents but is ineffective for the circulation part, and actually reduces system stability.

• Journal of Power Electronics
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• v.16 no.6
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• pp.2035-2044
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• 2016

In order to match the voltages between high voltage battery stacks and low voltage super-capacitors with a high conversion efficiency in hybrid energy sources electric vehicles (HESEVs), a high ratio bidirectional DC-DC converter with a synchronous rectification H-Bridge is proposed in this paper. The principles of high ratio step-down and step-up operations are analyzed. In terms of the bidirectional characteristic of the H-Bridge, the bidirectional synchronous rectification (SR) operation is presented without any extra hardware. Then the SR power switches can achieve zero voltage switching (ZVS) turn-on and turn-off during dead time, and the power conversion efficiency is improved compared to that of the diode rectification (DR) operation, as well as the utilization of power switches. Experimental results show that the proposed converter can operate bidirectionally in the wide ratio range of 3~10, when the low voltage continuously varies between 15V and 50V. The maximum efficiencies are 94.1% in the Buck mode, and 93.6% in the Boost mode. In addition, the corresponding largest efficiency variations between SR and DR operations are 4.8% and 3.4%. This converter is suitable for use as a power interface between the battery stacks and super-capacitors in HESEVs.

• Journal of Power Electronics
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• v.16 no.6
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• pp.1991-2004
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• 2016

An LC filter is required to reduce the output current ripple in the auxiliary resonant snubber inverter (ARSI) for high-performance applications. However, if the traditional control method is used in the ARSI with LC filter, then unnecessary current flows in the auxiliary circuit. In addressing this problem, a novel load-adaptive control that fully uses the filter inductor current ripple to realize the soft-switching of the main switches is proposed. Compared with the traditional control implemented in the ARSI with LC filter, the proposed control can reduce the required auxiliary current, contributing to higher efficiency and DC-link voltage utilization. In this study, the detailed circuit operation in the light load mode (LLM) and the heavy load mode (HLM) considering the inductor current ripple is described. The characteristics of the improved ARSI are expressed mathematically. A prototype with 200 kHz switching frequency, 80 V DC voltage, and 8 A maximum output current was developed to verify the effectiveness of the improved ARSI. The proposed ARSI was found to successfully operate in the LLM and HLM, achieving zero-voltage switching (ZVS) of the main switches and zero-current switching (ZCS) of the auxiliary switches from zero load to full load. The DC-link voltage utilization of the proposed control is 0.758, which is 0.022 higher than that of the traditional control. The peak efficiency is 91.75% at 8 A output current for the proposed control, higher than 89.73% for the traditional control. Meanwhile, the carrier harmonics is reduced from -44 dB to -66 dB through the addition of the LC filter.

• Journal of Power Electronics
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• v.16 no.3
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• pp.1226-1235
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• 2016

For wearable health monitoring systems, a fundamental problem is the limited space for storing energy, which can be translated into a short operational life. In this paper, a highly efficient active voltage doubling rectifier with a wide input range for micro-piezoelectric energy harvesting systems is proposed. To obtain a higher output voltage, the Dickson charge pump topology is chosen in this design. By replacing the passive diodes with unbalanced-biased comparator-controlled active counterparts, the proposed rectifier minimizes the voltage losses along the conduction path and solves the reverse leakage problem caused by conventional comparator-controlled active diodes. To improve the rectifier input voltage sensitivity and decrease the minimum operational input voltage, two low power common-gate comparators are introduced in the proposed design. To keep the comparator from oscillating, a positive feedback loop formed by the capacitor C is added to it. Based on the SMIC 0.18-μm standard CMOS process, the proposed rectifier is simulated and implemented. The area of the whole chip is 0.91×0.97 mm², while the rectifier core occupies only 13% of this area. The measured results show that the proposed rectifier can operate properly with input amplitudes ranging from 0.2 to 1.0V and with frequencies ranging from 20 to 3000 Hz. The proposed rectifier can achieve a 92.5% power conversion efficiency (PCE) with input amplitudes equal to 0.6 V at 200 Hz. The voltage conversion efficiency (VCE) is around 93% for input amplitudes greater than 0.3 V and load resistances larger than 20kΩ.