• Journal of Power Electronics
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• 제18권2호
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• pp.547-557
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• 2018

This work proposes a control method of frequency stabilization for grid integration of large-scale wind farms via the voltage source converter-based high-voltage direct current (VSC-HVDC) technology. First, the topology of grid integration of a large-scale wind farm via the VSC-HVDC link is provided, and simple control strategies for wind turbines, wind farm side VSC (WFVSC), and grid side VSC are presented. Second, a mathematical model between the phase angle of WFVSC and the frequency of the wind farm is established. The control principle of the large-scale wind power integrated system is analyzed in theory in accordance with the mathematical model. Third, frequency and AC voltage controllers of WFVSC are designed based on the mathematical model of the relationships between the phase angle of WFVSC and the frequency of the wind farm, and between the modulation index of WFVSC and the voltage of the wind farm. Corresponding controller structures are established by deriving a transfer function, and an optimization method for selecting the parameters of the frequency controller is presented. Finally, a case study is performed under different operating conditions by using the DIgSILENT/PowerFactory software. Results show that the proposed control method has good performance in the frequency stabilization of the large-scale wind power integrated system via the VSC-HVDC technology.

• Journal of Power Electronics
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• 제18권2호
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• pp.558-572
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• 2018

In addition to its modular nature, a Hybrid Modular Multilevel Converter (HMMC) assembled from half-bridge and full-bridge sub-modules, is able to block DC faults with a minimum number of switching devices, which makes it attractive for high power applications. This paper introduces a control strategy based on the Root-Least Square (RLS) algorithm to estimate the capacitor voltages instead of using direct measurements. This action eliminates the need for voltage transducers in the HMMC sub-modules and the associated communication link with the central controller. In addition to capacitor voltage balancing and suppression of circulating currents, a fault tolerant control unit (FTCU) is integrated into the proposed strategy to modify the parameters of the HMMC controller. On advantage of the proposed FTCU is that it does not need extra components. Furthermore, a fault detection unit is adapted by utilizing a hybrid estimation scheme to detect sub-module faults. The behavior of the suggested technique is assessed using PSCAD offline simulations. In addition, it is validated using a real-time digital simulator connected to a real time controller under various normal and fault conditions. The proposed strategy shows robust performance in terms of accuracy and time response since it succeeds in stabilizing the HMMC under faults.

• Journal of Power Electronics
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• 제18권2호
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• pp.511-521
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• 2018

Proportional capacitor current feedback active damping (CCFAD) has a limited valid damping region in the discrete time domain as (0, $f_s/6$. However, the resonance frequency ($f_r$) of an LCL-type filter is usually designed to be less than half the sampling frequency ($f_s$) with the symmetry regular sampling method. Therefore, ($f_s/6$, $f_s/2$) becomes an invalid damping region. This paper proposes an improved CCFAD method to extend the valid damping region from (0, $f_s/6$ to (0, $f_s/2$), which covers all of the possible resonance frequencies in the design procedure. The full-valid damping region is obtained and the stability margin of the system is analyzed in the discrete time domain with the Nyquist criterion. Results show that the system can operate stably with the proposed CCFAD method when the resonance frequency is in the region (0, $f_s/2$). The performances at the steady and dynamic state are enhanced by the selected feedback coefficient H and controller gain $K_p$. Finally, the feasibility and effectiveness of the proposed CCFAD method are verified by simulation and experimental results.

• Journal of Power Electronics
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• 제10권1호
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• pp.9-13
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• 2010

This paper proposes an input-series-output-parallel connected ZVS full bridge converter with interleaved control for photovoltaic power conditioning systems (PV PCS). The input-series connection enables a fully modular power-system architecture, where low voltage and standard power modules can be connected in any combination at the input and/or at the output, to realize any given specifications. Further, the input-series connection enables the use of low-voltage MOSFETs that are optimized for a very low RDSON, thus, resulting in lower conduction losses. The system costs decrease due to the reduced current, and the volumes of the output filters due to the interleaving technique. A topology for a photovoltaic (PV) dc/dc converter that can dramatically reduce the power rating and increase the efficiency of a PV system by analyzing the PV module characteristics is proposed. The control scheme, consisting of an output voltage loop, a current loop and input voltage balancing loops, is proposed to achieve input voltage sharing and output current sharing. The total PV system is implemented for a 10-kW PV power conditioning system (PCS). This system has a dc/dc converter with a 3.6-kW power rating. It is only one-third of the total PV PCS power. A 3.6-kW prototype PV dc/dc converter is introduced to experimentally verify the proposed topology. In addition, experimental results show that the proposed topology exhibits good performance.

• Journal of Power Electronics
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• 제13권5호
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• pp.766-778
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• 2013

The depletion of natural resources and renewable energy sources, such as photovoltaic (PV) energy, has been highlighted for global energy solution. The PV power control unit in the PV power-generation technology requires a high step-up DC-DC converter. The conventional step-up DC-DC converter has low efficiency and limited step-up ratio. To overcome these problems, a novel high step-up DC-DC converter using an isolated switched capacitor cell is proposed. The step-up converter uses the proposed transformer and employs the switched-capacitor cell to enable integration with the boost inductor. The output of the boost converter and isolated switched-capacitor cell are connected in series to obtain high step-up with low turn-on ratio. A hardware prototype with 30 V to 40 V input voltage and 340 V output voltage is implemented to verify the performance of the proposed converter. As an extended version, another novel high step-up isolated switched-capacitor single-ended DC-DC converter integrated with a tapped-inductor (TI) boost converter is proposed. The TI boost converter and isolated-switched-capacitor outputs are connected in series to achieve high step-up. All magnetic components are integrated in a single magnetic core to lower costs. A prototype hardware with 20 V to 40 V input voltage, 340 V output voltage, and 100 W output power is implemented to verify the performance of the proposed converter.

• Journal of Power Electronics
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• 제17권1호
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• pp.56-66
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• 2017

Fast and accurate fault detection is the primary step and one of the most important tasks in fault tolerant converters. In this paper, a fast and simple method is proposed to detect and diagnosis the faulty cell in a cascaded H-bridge multilevel inverter under a short circuit fault. In this method, the reference voltage is calculated using switching control pulses and DC-Link voltages. The comparison result of the output voltage and the reference voltage is used in conjunction with active cell pulses to detect the faulty cell. To achieve this goal, the cell which is active when the Fault signal turns to "0" is detected as the faulty cell. Furthermore, consideration of generating the active cell pulses is completely described. Since the main advantage of this method is its simplicity, it can be easily implemented in a programmable digital device. Experimental results obtained with an 11-level inverter prototype confirm the effectiveness of the proposed fault detection technique. In addition, they show that the diagnosis method is unaffected by variations of the modulation index.

• Journal of Power Electronics
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• 제17권1호
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• pp.222-231
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• 2017

In this paper, a new architecture for a cost-effective power conditioning systems (PCS) using a single-sourced asymmetric cascaded H-bridge multilevel inverter (MLI) for photovoltaic (PV) applications is proposed. The asymmetric MLI topology has a reduced number of parts compared to the symmetrical type for the same number of voltage level. However, the modulation index threshold related to the drop in the number of levels of the inverter output is higher than that of the symmetrical MLI. This problem results in a modulation index limitation which is relatively higher than that of the symmetrical MLI. Hence, an extra voltage pre-regulator becomes a necessary component in the PCS under a wide operating bias variation. In addition to pre-stage voltage regulation for the constant MLI dc-links, another auxiliary pre-regulator should provide isolation and voltage balance among the multiple H-bridge cells in the asymmetrical MLI as well as the symmetrical ones. The proposed PCS uses a single-ended DC-DC converter topology with a coupled inductor and charge-pump circuit to satisfy all of the aforementioned requirements. Since the proposed integrated-type voltage pre-regulator circuit uses only a single MOSFET switch and a single magnetic component, the size and cost of the PCS is an optimal trade-off. In addition, the voltage balance between the separate H-bridge cells is automatically maintained by the number of turns in the coupled inductor transformer regardless of the duty cycle, which eliminates the need for an extra voltage regulator for the auxiliary H-bridge in MLIs. The voltage balance is also maintained under the discontinuous conduction mode (DCM). Thus, the PCS is also operational during light load conditions. The proposed architecture can apply the module-integrated converter (MIC) concept to perform distributed MPPT. The proposed architecture is analyzed and verified for a 7-level asymmetric MLI, using simulation results and a hardware implementation.

• Journal of Power Electronics
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• 제17권1호
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• pp.136-148
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• 2017

In recent years, voltage source multilevel converters are very popular in medium/high-voltage industrial applications, among which the NPC/H-Bridge converter is a popular solution to the medium/high-voltage drive systems. The conventional finite control set model predictive control (FCS-MPC) strategy is not practical for multilevel converters due to their substantial calculation requirements, especially under high number of voltage levels. To solve this problem, a hierarchical model predictive voltage control (HMPVC) strategy with referring to the implementation of g-h coordinate space vector modulation (SVM) is proposed. By the hierarchical structure of different cost functions, load currents can be controlled well and common mode voltage can be maintained at low values. The proposed strategy could be easily expanded to the systems with high number of voltage levels while the amount of required calculation is significantly reduced and the advantages of the conventional FCS-MPC strategy are reserved. In addition, a HMPVC-based field oriented control scheme is applied to a drive system with the NPC/H-Bridge converter. Both steady-state and transient performances are evaluated by simulations and experiments with a down-scaled NPC/H-Bridge converter prototype under various conditions, which validate the proposed HMPVC strategy.

• Journal of Power Electronics
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• 제16권5호
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• pp.1904-1917
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• 2016

The moving average filter (MAF) is widely utilized to improve the disturbance rejection capability of phase-locked loops (PLLs). This is of vital significance for the grid-integration and stable operation of power electronic converters to electric power systems. However, the open-loop bandwidth is drastically reduced after incorporating a MAF into the PLL structure, which makes the dynamic response sluggish. To overcome this shortcoming, some new techniques have recently been proposed to improve the transient response of MAF-based PLLs. In this paper, a comprehensive performance comparison of advanced MAF-based PLL algorithms is presented. This comparison includes HPLL, MPLC-PLL, QT1-PLL, and DMAF-PLL. Various disturbances, such as grid voltage sag, voltage flicker, harmonics distortion, phase-angle and frequency jumps, DC offsets and noise, are considered to experimentally test the dynamic performances of these PLL algorithms. Finally, an improved positive sequence extraction method for a HPLL under the frequency jumps scenario is presented to compensate for the steady-state error caused by non-frequency adaptive DSC, and a satisfactory performance has been achieved.

• Journal of Power Electronics
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• 제16권5호
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• pp.1964-1980
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• 2016

This paper presents a new simplified harmonics extraction algorithm based on the synchronous reference frame (SRF) for an indirect current controlled (ICC) three-level neutral point diode clamped (NPC) inverter-based shunt active power filter (SAPF). The shunt APF is widely accepted as one of the most effective current harmonics mitigation tools due to its superior adaptability in dynamic state conditions. In its controller, the SRF algorithm which is derived based on the direct-quadrature (DQ) theory has played a significant role as a harmonics extraction algorithm due to its simple implementation features. However, it suffers from significant delays due to its dependency on a numerical filter and unnecessary computation workloads. Moreover, the algorithm is mostly implemented for the direct current controlled (DCC) based SAPF which operates based on a non-sinusoidal reference current. This degrades the mitigation performances since the DCC based operation does not possess exact information on the actual source current which suffers from switching ripples problems. Therefore, three major improvements are introduced which include the development of a mathematical based fundamental component identifier to replace the numerical filter, the removal of redundant features, and the generation of a sinusoidal reference current. The proposed algorithm is developed and evaluated in MATLAB / Simulink. A laboratory prototype utilizing a TMS320F28335 digital signal processor (DSP) is also implemented to validate effectiveness of the proposed algorithm. Both simulation and experimental results are presented. They show significant improvements in terms of total harmonic distortion (THD) and dynamic response when compared to a conventional SRF algorithm.